A new full swing full adder based on a new logic approach, MH Ghadiry, M Nadisenejani

Tags: power consumption, full adder, transistors, IEEE Trans, full-swing, power, Islamic Azad University, input patterns, supply voltage, worst-case propagation delay, output load, SERF, COUT, XOR-XNOR, Department of Computer Engineering, power supply, logic approach, transistor count, module
Content: World Applied Sciences Journal 11 (7): 808-812, 2010 ISSN 1818-4952 © IDOSI Publications, 2010 A New Full Swing Full Adder Based on a New Logic Approach
1M.H. Ghadiry, 2M. Nadisenejani and 1M. Miryahyaei
1Department of Computer Engineering, Islamic Azad University, Arak Branch, Arak, Iran 2Department of Computer Engineering, Islamic Azad University, Ashtian Branch, Ashtian, Iran
Abstract: This paper presents a new low power full adder based on a new logic approach, which reduces power consumption by implementing full adder using only one XOR module. In addition, output inverters have been embedded in the full adder cell, which boost driving capability, reduce delay and provide complementary outputs. Simulation has been carried out by HSPICE in 0.18µm bulk technology at 1.8V supply voltage. The results show that the proposed circuit has less power and PDP than recently proposed full adders in the literature. key words: Full adder Low Power Performance Logic approach CMOS VLSI
INTRODUCTION One of the most important issues in VLSI Design is power consumption. With the continuously increasing chips' complexity and number of transistors in a chip, circuits' power consumption is growing as well. Higher power consumption, raises chips' temperature and directly affect battery life in portable devices as it causes more current to be withdrawn from the power supply. High temperature afflicts circuit operation and reliability so requires more complicated cooling and packaging techniques [1]. Full adder is the fundamental unit in circuits used for performing arithmetic operations such as multipliers, compressors, large adders, comparators and parity checkers [2]. Therefore, reducing power consumption in full adders, will reduce the overall power consumption of the whole system. There are several issues related to the full adders. Some of them are power consumption, performance, area, noise immunity, regularity and good driving ability [3]. Several works have been done in order to decrease transistor count and consequently decrease power consumption and area [3-6]. In some designs, reducing transistor count has been resulted in threshold loss problem that causes non-full swing outputs [2-3, 7], low speed and low noise immunity especially when they are used in cascaded fashion. The aim of this study is to design 1-bit low-power full adder cell, based on a new logic approach without losing driving capability.
previous works Review: There is a variety of full adders in the literature for example there are 41 full adders only in [2]. Many of them use XOR and XNOR as intermediate signals [8-9]. There are full adders based on only multiplexers or inverters. In terms of transistor count, it varies from 6 in [4] up to 32 in TFA [10]. There are full adders in dynamic style, such as [5, 11] and current mode [4]. Including analysis of all full adders in this study is not possible. Thus, six well-known full adders with various numbers of transistors have been selected in order to study and compare with the proposed full adder cell. Conventional CMOS [12] full adder in Fig.1 (a) with 28 transistors is a robust, high power and area full adder, which has been designed, based on standard CMOS topology. It has full-swing outputs that increase noise margin and reliability. Due to high number of transistors, its power consumption is high. Large PMOS Transistor in pull up network result in high input capacitances, which cause high delay and dynamic power. However, using inverters on the output nodes decreases the rise-time and fall-time and increases the driving ability. It functions well at low power supply voltages because it does not have threshold loss problem. SERF full adder, as shown in Fig. 1 (b), uses energy recovery technique to reduce power consumption [13]. Ten transistors are used to implement this circuit. Thus, it is low-cost and low-area cell. On the other hand, outputs are not full-swing. Thus, it cannot work correctly at low voltages and it exhibits high delay when the cells are cascaded to make large full circuits.
Corresponding Author: M.H. Ghadiry, Department of Computer Engineering, Islamic Azad University, Arak Branch, Arak, Iran. E-mail: [email protected] 808
World Appl. Sci. J., 11 (7): 808-812, 2010
(b) (a)
(d) (c)
(e)
(f) Fig. 1: Several full adder cells from the literature. (a) CCMOS. (b) Energy recovery full adder (SERF). (c) New version of 14T (N14T). (d) 16T. (e) Multiplexer based full adder (MB12T). (f)New version of hybrid pass logic with static output drive full adder (26T).
New-14T, Fig. 1 (c), is an improvemnet from 14T [14]. which has simultaneous XOR and XNOR signals. Feedback transistors provide rail-to-rail outputs in XOR-XNOR module. However, they prompt high delay. Fig. 1 (d) shows another improvemed version from 14T, which is called 16T [15]. It is the same as New-14T in terms of the output modules. However, the XOR-XNOR module has been modified to reduce delay and power consumption. lower power and delay has been obtained at the expense of 2 additional transistors. The XOR-XNOR modules does not have full-swing outputs thus, the transistors which have been connected to this module are turned on or off slowly.
MB12T [16] has been implemented using six multiplexers and 12 transistors. Each multiplexer is implemented by pass-transistor logic with two transistors. As shown in Fig. 1 (e), there is no VDD or GND connection in this circuit. Therefore, short circuit power can be decreased significantly. However, pass gates lack of driving in cascaded mode and high fan-out that leads to high delay. 26T full adder [9] in Fig. 1 (f), has used the output module of CCMOS for generating COUT signal and also modified version of SUM generator circuit of 16T with additional inverters in order to increase driving ability and performance. The XOR-XNOR module is the same modoule as 16T, with two additional feedback transistors
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World Appl. Sci. J., 11 (7): 808-812, 2010
Table 1: Truth table for the proposed structures
C
B
A
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
An Alternative Logic Approach: By replacing the logic 0
and 1 with the equivalent inputs at each case of input,
0
several tables like Table 1 can be produced. Proper
0
categorizing will result in reduction in number of gates
1
and power. Table 1 shows that implementing both COUT
1
and SUM based on signal B C make it possible to
1
generate them using only A and C inputs. The new logic
1
approach reduces the power consumption by eliminating
0
power-consuming XNOR gate.
0
In order to increase the driving ability for high fan-
out applications, output inverters are embedded in the
circuit by implementing COUT and SUM . Fig. 2 shows the
proposed logic approach.
Fig. 2: The proposed logic to implement 1-bit full adder cell with one XOR gate
The Proposed Full Adder Cell (SS16T): Fig. 3 shows the transistor realization of the cell. A full-swing XOR gate from [8] has been used in this full adder. It uses 6 transistors and benefits from full-swing output, low delay and power consumption. Two inverters in the path between CIN and COUT act as a buffer decreasing the propagation delay. Multiplexers are implemented using pass gates with only two transistors. Full-swing XOR module avoids double VT threshold loss problem at the input node of the output inverters and high leakage power consumption in the output inverters as well.
Fig. 3: The proposed full adder cell (SS16T) to make outputs full swing. It is a high-performance and low-power XOR-XNOR module with full-swing outputs. This design trades power and performance with area. All the intermediate signals are rail-to-rail and the outputs have good driving capability. Therefore, it shows high performance in cascaded fashion and large loads. Using both VDD and GND connection for generating COUT causes to speed up in carry propagation. Pass gate design together with full-swing signals reduce the leakage and short-circuit current and make it a low power circuit. Proposed Full Adder: In this section, first, a new logic approach to design low power full adder is proposed. Afterward the proposed full adder will be illustrated.
Simulation Setup: All the netlists have been simulated using HSPICE in 0.18µm bulk technology. Each input is derived by two cascaded inverters. Two capacitances are used as loads for COUT and SUM connections. Power and delay of the inverters are included in the power and delay calculation of the whole circuit. To study the properties of the compared circuits in cascaded fashion, 4-bit ripple carry adder (RCA) has been implemented. The performance of the under test circuits have been evaluated in terms of worst-case propagation delay. Propagation delay has been calculated from 50% of voltage level of input to 50% of voltage level of output. In this study, power means the total average power consumption. Power delay product (PDP) has been calculated from production of worst-case delay and average power consumption. Transistors' size has been optimized in order to minimize the PDP. To compare the cells, several input patterns have to been applied to cover all the input cases. An input pattern, which maximizes the power consumption for a given cell, could exhibit less power consumption for another cell. Different patterns also show different delays. With three inputs and three frequencies, there are 27 different input patterns. All the 27 input patterns have been applied to the under test circuits to fairly compare them [15].
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World Appl. Sci. J., 11 (7): 808-812, 2010
(a)
(d)
(b)
(e)
(c)
(f)
Fig. 5: Power and delay comparison vs. supply voltage, output load and frequency. (a) Power consumption vs. supply voltage. (b) Power consumption vs. output load (c) Delay vs. supply voltage (d) Delay vs. output load (e) PDP vs. supply voltage (f) PDP vs. output load.
RESULTS AND DISCUSSION Fig. 5 (a), (b) and (c) shows power consumption, delay and PDP vs. supply voltage. It starts from 1V to 1.8V. Both 26T and SS16T have less power consumption than other four circuits and SS16T's power consumption is less than 26T. SERF does not function properly at 1V, therefore, there is no mark for SERF at this voltage. Although, SS16T shows higher delay than 26T, its PDP still is less than 26T. CCMOS and SERF are behind 26T and SS16T in terms of PDP. Fig. 5 (d), (e) and (f), demonstrate the effect of output load on power, delay and PDP respectively. As load increases power, delay and PDP increase as well. The gap between those circuits, which drive the loads thorough
inverts and those which not, widens as load increases. 26T, SS16T and CCMOS show noticeably less delay than MB12T, SERF, 16T and N14T. SS16T's delay is higher than 26T due to non full-swing signals of multiplexers that drive output inverters. N14T and SERF have highest PDP followed by the next group containing CCMOS, 16T and MB12T. In order to have a closer comparison, the values obtained from simulation at 1.8V and 10fF output load have been brought in Table 2. They have been sorted based on power consumption. The first circuit in power ranking is SS16T with 63 µW. However, it is not a very good choice for high-speed applications. 26T has higher power consumption and performance than SS16T. Considering PDP, the superior circuit is SS16T.
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World Appl. Sci. J., 11 (7): 808-812, 2010
Table 2: simulation results for 1.8V, 10fF and 100MHz
PWR
DLY
PDP
Circuit
(uW)
(ns)
(e-15)
SS16T
63
0.56
36.5
26T
69
0.55
37.9
MB12T
72
0.79
56.8
16T
80
0.73
58.4
NEW14T
98
0.74
72.5
SERF
121
0.63
76.2
CCMOS
161
0.61
98.2
Max. Freq. (GHz) 1.72 1.82 1.27 1.37 1.35 1.59 1.64
All the other circuits have higher PDP than 26T and SS16T. In addition to power and delay, maximum frequency has been calculated based on delay. Apparently, 26T obtained highest frequency. For normal applications, which the main aim is to get lowest PDP, SS16T is a proper circuit. CONCLUSION A full-swing full adder cell based on a new logic approach was proposed in this paper. The new full adder employed one XOR gate as intermediate signal in order to reduce number of gates and power consumption. It has complementary outputs and output inverters to increase driving ability. The proposed circuit was simulated using HSPICE and compared to several full adders in the literature. The results show that there are improvements in terms of power consumption and PDP compared to simulated circuits. In addition, simulation for high output loads show that full-swing full adders with output inverters have less delay than those circuits using no output inverter or with non-full swing outputs. Furthermore, the study shows that, lowering the number of transistors does not always mean power reduction. REFERENCES 1. Shams, A.M. and Gu. M. Zhang, 2005. A review of 0.18um full adder performances for tree structure arithmetic circuits, IEEE Trans. Very Large Scale Integration (VLSI) Syst, 13(6): 686-695. 2. Bui, H.T., Y. Wang and Y. Jiang, 2002. Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates, IEEE Trans. Circuits Systems-II: Analog Digit. Signal Process, 49(1): 25-30. 3. Jin-Fa, Yin-Tsung Hwng, Ming-Hwa Sheu, ChengChe Ho, 2007. A novel high-speed and energy efficient 10-transistor full adder design, IEEE Tran. on Circuits and Systems-II: Express Briefs, 54: 1050-1059.
4. Navi, K., V. Foroutan, B. Mazloomnejad, Sh. Bahrololoumi, O. Hashempour and M. Haghparast, 2008. A six transistors full adder, World Appl. Sci. J., 4(1): 142-149. 5. Nadi, M., M. Senejani and M. Hosseinghadiry, 2009. Miryahyaei, Low dynamic power high performance full adder, in Proc. of ICFCC. pp: 482-486. 6. Foroutan, V., K. Navi and Majid Haghparast, 2008. A new low power dynamic full adder cell based on majority function, World Appl. Sci. J, 4(1): 133-141. 7. Veeramachaneni, S. and M.B. Sirinivas, 2008. New improved 1-bit full adder cells, Proc. of CCECE/CGEI, pp: 735-738. 8. Ghadiry, M.H., Abu Khari A'Ain and M. Nadisenejani, 2011. Design and analysis of a novel low PDP full adder cell, Submitted for publication in J. Circuits, Systems and Computers, pp: 20(3). 9. Goel, S., A. Kumar and M.A. Bayoumi, 2006. Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style, IEEE Trans. on VLSI Systems, 14(12): 1309-1321. 10. Douglas A. Pucknell and Kamram Eshraghian, 1994. Basic VLSI design. 11. Navarro-Botello, V., J.A. Montiel-Nelson and S. Nooshabadi, 2007. High performance low power CMOS dynamic logic for arithmetic Circuits, Microelectronics J., 38(1): 482-488. 12. Navi, K., M. Maeen, V. Foroutan, S. Timarchi and O. Kavei, 2009. A novel low power full-adder cell for low voltage, Integration the VLSI J., 42(4): 457-467. 13. Shalem, R., E. John and L.K. John, 1999. A novel lowpower energy recovery full adder cell, Proc. of GLSVLSI, 1: 380-383. 14. Shams, A.M. and M.A. Bayoumi, 2000. A novel high performance CMOS 1-bit full adder cell, IEEE Trans. Circuits and Systems-II: Analog digital signal Process, 47(5): 478-481. 15. Shams, A.M., T.K. Darwish and M.A. Bayoumi, 2002. Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. on Very Large Scale integration systems, 10(1): 20-29. 16. Jiang, Y., A Al-Sheraidah, Y. Wang, E. Sha and J. Chung, 2004. A novel multiplexer-based low power full adder", IEEE Tran. On Circuits and Systems-II: Express Briefs, 51(7): 345-348.
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