VLSI technology, MTIYI Sem

Tags: TECHNOLOGICAL SCIENCES, M. Tech, UGC-AUTONOMOUS, VLSI Design, REFERENCE BOOKS, TEXT BOOKS, Pearson Education, Circuit Design, Primitives, Genetic Algorithms, Design programs, Ad Hoc Wireless Networks, MOS Transistor, Simulation, CMOS, Digital Design, Image Processing, Wireless Sensor Networks, Wireless Networks, Core Course, Processor Micro Architecture, Finite State Machines, MOS Transistor Technology, Analog Integrated Circuit Design, Pull Gates, Analog Integrated Circuit Design CMOS Digital Integrated Circuit Design, Ashish Srivastava, System Architecture, fault simulation, design for testability, CMOS Inverter, Rapid Prototyping, placement and routing, layout design rules, Michael J. Flynn, Digital Signal Processing, Digital Integrated Circuit Design, Truevalue Simulation, Mentor Graphics, Precharge and Equalization Circuit, Serial Binary Adder, Analog Integrated Circuit, SelfRefresh Circuit, Transistor-level design, Kluwer Academic Press, Analog Circuit, Digital System Design, design styles, CMOS VLSI Circuit Design, VLSI LABORATORY, Power Dissipation, Wiley Interscience, Testability CMOS Mixed Signal Circuit Design Digital Signal Processors, VLSI Circuit Design, Oxford University Press, Layout Design, Addison Wesley Professional, PHYSICAL DESIGN AUTOMATION, John Wiley Student Edition, Embedded Systems, Sensor Networks, Design Automation, Algorithms for VLSI Design Automation, Communication Interfaces, Genetic Algorithm, John Wiley, Communication Interface, Reliable Digital Transmission, Majority logic decoding, Hamming Codes, Error control, Convolutional Codes, Routing Protocols, MAC Protocols, Cyclic Codes, Syndrome Decoding, Transport Layer Protocol, Sensor Network, Transport Layer, Neural Network, Mathematical Foundation, VERILOG HDL, Design Methodology, Design methodologies, Cache Organization, Sequential Behavior, automatic test pattern generation, Sequential Udps, ASIC DESIGN UNIT, Assignments, LOGIC SYNTHESIS, Sequential Logic Synthesis, Algorithms, Back Propagation Network, Physical Design cycle, Neural Networks, Modelling and Simulation, Propagation Delay, Synthesis Methodology, Verilog Models, HARDWARE DESCRIPTION LANGUAGES UNIT, standard cell
Content: JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS)
I Year ­ I Semester Category
M.Tech. (VLSI DESIGN) COURSE STRUCTURE AND SYLLABUS Course Title
Core Course I Core Course II Core Course III
VLSI Technology CMOS Analog Integrated Circuit Design CMOS Digital Integrated Circuit Design
Int. Ext. L P C marks marks 40 60 4 -- 4 40 60 4 -- 4 40 60 4 -- 4
Core Elective I Core Elective II
Digital System Design Hardware Software Co-Design CPLD and FPGA Architectures and Applications Algorithms for VLSI Design Automation embedded system Design Device Modeling
4 -- 4 40 60 4 -- 4 40 60
Open Elective I Laboratory I Seminar I
Soft Computing Techniques Image and Video processing Software Defined Radio VLSI Laboratory ­ I Seminar Total Credits
4 -- 4 40 60
40 60 -- 4 2
50
-- -- 4 2
24 8 28
I Year ­ II Semester Category
Course Title
Core Course IV Core Course V Core Course VI Core Elective III Core Elective IV Open Elective II Laboratory II Seminar II Total Credits
Low Power VLSI Design Design for Testability CMOS Mixed Signal Circuit Design Digital Signal Processors and Architectures ASIC Design Hardware Description Language Optimization Techniques in VLSI Design System On Chip Architecture Semiconductor Memory Design and Testing Scripting Languages Coding Theory and Techniques Adhoc Wireless Networks VLSI Laboratory ­ II Seminar
Int. Ext. L P C marks marks 40 60 4 -- 4 40 60 4 -- 4 40 60 4 -- 4 40 60 4 -- 4
40 60 4 -- 4
40 60 4 -- 4
40 60 -- 4 2
50
-- -- 4 2
24 8 28
II Year - I Semester Comprehensive Viva-Voce Project work Review I
Course Title Total Credits
Int. Ext. L P C
marks Marks
-- 100 -- -- 4
50
-- -- 24 12
-- 24 16
II Year - II Semester
Course Title
Project work Review II Project Evaluation (Viva-Voce) Total Credits
Int. Ext. L P C
marks Marks
50
-- -- 8 4
-- 150 -- 16 12
-- 24 16
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) VLSI TECHNOLOGY UNIT ­I: Review of Microelectronics and Introduction to MOS Technologies: MOS, CMOS, BiCMOS Technology. Basic Electrical Properties of MOS, CMOS & BiCMOS Circuits: Ids ­ Vds relationships, Threshold Voltage VT, Gm, Gds and o, Pass Transistor, MOS, CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model, Latch-up in CMOS circuits. UNIT ­II: Layout Design and Tools: Transistor structures, Wires and Vias, Scalable Design rules, Layout Design tools. Logic Gates & Layouts: Static Complementary Gates, Switch Logic, Alternative Gate circuits, Low power gates, Resistive and Inductive interconnect delays. UNIT ­III: Overview of semiconductor industry, Stages of Manufacturing, Process and product trends, Crystal growth, Basic wafer fabrication operations, process yields, Semiconductor material preparation, Basic wafer fabrication operations, Yield measurement, Contamination sources, Clean room construction, Oxidation and Photolithography, Doping and Depositions, Metallization. Ten step patterning process, Photoresists, physical properties of photoresists, Storage and control of photoresists, photo masking process, Hard bake, develop inspect, Dry etching Wet etching, resist stripping UNIT ­IV Doping and depositions: Diffusion process steps, deposition, Drive-in oxidation, Ion implantation-1, Ion implantation-2, CVD basics, CVD process steps, Low pressure CVD systems, Plasma enhanced CVD systems, Vapour phase epitoxy, molecular beam epitaxy. UNIT ­V Design rules and Scaling, BICMOS ICs: Choice of transistor types, pnp transistors, Resistors, capacitors, Packaging: Chip characteristics, package functions, package operations TEXT BOOKS: 1. Peter Van Zant, Microchip fabrication, McGraw Hill, 1997. 2. C.Y. Chang and S.M. Sze, ULSI technology, McGraw Hill, 2000 REFERENCE BOOKS: 1. Micro Electronics circuits Analysis and Design 2nd Edition, Muhammad H Rashid, CENAGE Learning2011. 2. Eugene D. Fabricius, Introduction to VLSI design, McGraw Hill, 1999 3. Wani-Kai Chen (editor), The VLSI Hand book, CRI/IEEE press, 2000 4. S.K. Gandhi, VLSI Fabrication principles, John Wiley and Sons, NY, 1994
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) CMOS ANALOG INTEGRATED CIRCUIT DESIGN UNIT -I: MOS Devices and Modeling The MOS Transistor, Passive Components- Capacitor & Resistor, Integrated circuit Layout, CMOS Device Modeling - Simple MOS Large-Signal Model, Other Model Parameters, Small-Signal Model for the MOS Transistor, Computer simulation models, Sub-threshold MOS Model. UNIT -II: Analog CMOS Sub-Circuits: MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks and Sources, Current Mirrors-Current mirror with Beta Helper, Degeneration, Cascode current Mirror and Wilson Current Mirror, Current and Voltage References, Band gap Reference. UNIT -III CMOS Amplifiers: Inverters, Differential Amplifiers, Cascode Amplifiers, Current Amplifiers, Output Amplifiers, High Gain Amplifiers Architectures. UNIT -IV CMOS Operational Amplifiers: Design of CMOS Op Amps, Compensation of Op Amps, Design of Two-Stage Op Amps, PowerSupply Rejection Ratio of Two-Stage Op Amps, Cascode Op Amps, Measurement Techniques of OP Amp. UNIT -V Comparators: Characterization of Comparator, Two-Stage, Open-Loop Comparators, Other Open-Loop Comparators, Improving the Performance of Open-Loop Comparators, Discrete-Time Comparators. TEXT BOOKS: CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University Press, International Second Edition/Indian Edition, 2010. Analysis and Design of Analog Integrated Circuits- Paul R. Gray, Paul J. Hurst, S. Lewis and R. G. Meyer, Wiley India, Fifth Edition, 2010. REFERENCE BOOKS: Analog Integrated Circuit Design- David A. Johns, Ken Martin, Wiley Student Edn, 2013. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition. CMOS: Circuit Design, Layout and Simulation- Baker, Li and Boyce, PHI.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) CMOS DIGITAL INTEGRATED CIRCUIT DESIGN UNIT ­I: MOS Design: Pseudo NMOS Logic ­ Inverter, Inverter threshold voltage, Output high voltage, Output Low voltage, Gain at gate threshold voltage, Transient response, Rise time, Fall time, Pseudo NMOS logic gates, Transistor equivalency, CMOS Inverter logic. UNIT ­II: Combinational MOS Logic Circuits: MOS logic circuits with NMOS loads, Primitive CMOS logic gates ­ NOR & NAND gate, Complex Logic circuits design ­ Realizing Boolean expressions using NMOS gates and CMOS gates , AOI and OIA gates, CMOS full adder, CMOS transmission gates, Designing with Transmission gates. UNIT ­III: Sequential MOS Logic Circuits: Behavior of bistable elements, SR Latch, Clocked latch and flip flop circuits, CMOS D latch and edge triggered flipflop. UNIT ­IV: Dynamic Logic Circuits: Basic principle, Voltage Bootstrapping, Synchronous dynamic pass transistor circuits, Dynamic CMOS transmission gate logic, High performance Dynamic CMOS circuits. UNIT ­V: Semiconductor Memories: Types, RAM array organization, DRAM ­ Types, Operation, Leakage currents in DRAM cell and refresh operation, SRAM operation Leakage currents in SRAM cells, Flash Memory- NOR flash and NAND flash. TEXT BOOKS: 1. Digital Integrated Circuit Design ­ Ken Martin, Oxford University Press, 2011. 2. CMOS Digital Integrated Circuits Analysis and Design ­ Sung-Mo Kang, Yusuf Leblebici, TMH, 3rd Ed., 2011. REFERENCE BOOKS: 1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective ­ Ming-BO Lin, CRC Press, 2011 2. Digital Integrated Circuits ­ A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, 2nd Ed., PHI.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem(VLSI Design) DIGITAL SYSTEM DESIGN (Core Elective ­I) UNIT -I: Minimization and Transformation of Sequential Machines: The Finite State Model ­ Capabilities and limitations of FSM ­ State equivalence and machine minimization ­ Simplification of incompletely specified machines. Fundamental mode model ­ Flow table ­ State reduction ­ Minimal closed covers ­ Races, Cycles and Hazards. UNIT -II: Digital Design: Digital Design Using ROMs, PALs and PLAs , BCD Adder, 32 ­ bit adder, State graphs for control circuits, Scoreboard and Controller, A shift and add multiplier, Array multiplier, Keypad Scanner, Binary divider. UNIT -III: SM Charts: State machine charts, Derivation of SM Charts, Realization of SM Chart, Implementation of Binary Multiplier, dice game controller. UNIT -IV: Fault Modeling & Test Pattern Generation: Logic Fault model ­ Fault detection & Redundancy- Fault equivalence and fault location ­Fault dominance ­ Single stuck at fault model ­ Multiple stuck at fault models ­Bridging fault model. Fault diagnosis of combinational circuits by conventional methods ­ Path sensitization techniques, Boolean Difference method ­ Kohavi algorithm ­ Test algorithms ­ D algorithm, PODEM, Random testing, Transition count testing, Signature analysis and test bridging faults. UNIT -V: Fault Diagnosis in Sequential Circuits: Circuit Test Approach, Transition Check Approach ­ State identification and fault detection experiment, Machine identification, Design of fault detection experiment TEXT BOOKS: 1. Fundamentals of Logic Design ­ Charles H. Roth, 5th Ed., Cengage Learning. 2. Digital Systems Testing and Testable Design ­ Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman- John Wiley & Sons Inc. 3. Logic Design Theory ­ N. N. Biswas, PHI REFERENCE BOOKS: 1. Switching and Finite Automata Theory ­ Z. Kohavi , 2nd Ed., 2001, TMH 2. Digital Design ­ Morris Mano, M.D.Ciletti, 4th Edition, PHI. 3. Digital Circuits and Logic Design ­ Samuel C. Lee , PHI
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) HARDWARE - SOFTWARE CO-DESIGN (Core Elective ­I) UNIT ­I: Co- Design Issues: Co- Design Models, Architectures, Languages, A Generic Co-design Methodology. Co- Synthesis Algorithms: Hardware software synthesis algorithms: hardware ­ software partitioning distributed system cosynthesis. UNIT ­II: Prototyping and Emulation: Prototyping and emulation techniques, prototyping and emulation environments, future developments in emulation and prototyping architecture specialization techniques, system communication infrastructure Target Architectures: Architecture Specialization techniques, System Communication infrastructure, Target Architecture and Application System classes, Architecture for control dominated systems (8051-Architectures for High performance control), Architecture for Data dominated systems (ADSP21060, TMS320C60), Mixed Systems. UNIT ­III: Compilation Techniques and Tools for Embedded Processor Architectures: Modern embedded architectures, embedded software development needs, compilation technologies, practical consideration in a compiler development environment. UNIT ­IV: Design Specification and Verification: Design, co-design, the co-design computational model, concurrency coordinating concurrent computations, interfacing components, design verification, implementation verification, verification tools, interface verification UNIT ­V: Languages for System ­ Level Specification and Design-I: System ­ level specification, design representation for system level synthesis, system level specification languages, Languages for System ­ Level Specification and Design-II: Heterogeneous specifications and multi language co-simulation, the cosyma system and lycos system. TEXT BOOKS: 1. Hardware / Software Co- Design Principles and Practice ­ Jorgen Staunstrup, Wayne Wolf ­ 2009, Springer. 2. Hardware / Software Co- Design - Giovanni De Micheli, Mariagiovanna Sami, 2002, Kluwer Academic Publishers REFERENCE BOOKS: 1. A Practical Introduction to Hardware/Software Co-design -Patrick R. Schaumont - 2010 ­ Springer
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) CPLD AND FPGA ARCHITECURES AND APPLICATIONS (Core Elective ­I) UNIT-I: Introduction to Programmable Logic Devices: Introduction, Simple Programmable Logic Devices ­ Read Only Memories, Programmable Logic Arrays, Programmable Array Logic, Programmable Logic Devices/Generic Array Logic; Complex Programmable Logic Devices ­ Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation. UNIT-II: Field Programmable Gate Arrays: Organization of FPGAs, FPGA Programming Technologies, Programmable Logic Block Architectures, Programmable Interconnects, Programmable I/O blocks in FPGAs, Dedicated Specialized Components of FPGAs, Applications of FPGAs. UNIT -III: SRAM Programmable FPGAs: Introduction, Programming Technology, Device Architecture, The Xilinx XC2000, XC3000 and XC4000 Architectures. UNIT -IV: Anti-Fuse Programmed FPGAs: Introduction, Programming Technology, Device Architecture, The Actel ACT1, ACT2 and ACT3 Architectures. UNIT -V: Design Applications: General Design Issues, Counter Examples, A Fast Video Controller, A Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT devices, Designing Adders and Accumulators with the ACT Architecture. TEXT BOOKS: 1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International Edition. 2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage Learning. REFERENCE BOOKS: 1. Field Programmable Gate Arrays - John V. Oldfield, Richard C. Dorf, Wiley India. 2. Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/Samiha Mourad, Pearson Low Price Edition. 3. Digital Systems Design with FPGAs and CPLDs - Ian Grout, Elsevier, Newnes. 4. FPGA based System Design - Wayne Wolf, Prentice Hall Modern Semiconductor Design Series.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design)
ALGORITHMS FOR VLSI DESIGN AUTOMATION
UNIT I PRELIMINARIES
(Core Elective ­II)
Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Computational complexity, Tractable and intractable problems.
UNIT II GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, genetic algorithms.
UNIT III LAYOUT COMPACTION, PLACEMENT, FLOORPLANNING AND ROUTING Problems, Concepts and Algorithms. MODELLING AND SIMULATION Gate Level Modelling and Simulation, Switch level Modelling and Simulation.
UNIT IV LOGIC SYNTHESIS AND VERIFICATION Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis HIGH-LEVEL SYNTHESIS Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level Transformations. UNIT V PHYSICAL DESIGN AUTOMATION OF FPGAs FPGA technologies, Physical Design cycle for FPGAs, partitioning and Routing for segmented and staggered Models. PHYSICAL DESIGN AUTOMATION OF MCMs MCM technologies, MCM physical design cycle, Partitioning, Placement - Chip Array based and Full Custom Approaches, Routing ­ Maze routing, Multiple stage routing, Topologic routing, Integrated Pin ­ Distribution and routing, Routing and Programmable MCMs.
TEXT BOOKS
1. Algorithms for VLSI Design Automation, S.H.Gerez, 1999, WILEY Student Edition, John wiley & Sons (Asia) Pvt. Ltd. 2. Algorithms for VLSI Physical Design Automation ­ Naveed Sherwani, 3rd Ed., 2005, Springer International Edition. REFERENCE BOOKS
1. Computer Aided Logical Design with Emphasis on VLSI ­ Hill & Peterson, 1993, Wiley. 2. Modern VLSI Design:Systems on silicon ­ Wayne Wolf, 2nd ed., 1998, Pearson Education Asia.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) EMBEDDED SYSTEMS DESIGN (Core Elective ­II) UNIT -I: Introduction to Embedded Systems Definition of Embedded System, Embedded Systems Vs General Computing Systems, History of Embedded Systems, Classification, Major Application Areas, Purpose of Embedded Systems, Characteristics and Quality Attributes of Embedded Systems. UNIT -II: Typical Embedded System: Core of the Embedded System: General Purpose and Domain Specific Processors, ASICs, PLDs, Commercial Off-The-Shelf Components (COTS), Memory: ROM, RAM, Memory according to the type of Interface, Memory Shadowing, Memory selection for Embedded Systems, Sensors and Actuators, Communication Interface: Onboard and External Communication Interfaces. UNIT -III: Embedded Firmware: Reset Circuit, Brown-out Protection Circuit, Oscillator Unit, Real Time Clock, Watchdog Timer, Embedded Firmware Design Approaches and Development Languages. UNIT -IV: RTOS Based Embedded System Design: Operating System Basics, Types of Operating Systems, Tasks, Process and Threads, Multiprocessing and Multitasking, Task Scheduling. UNIT -V: Task Communication: Shared Memory, Message Passing, Remote Procedure Call and Sockets, Task Synchronization: Task Communication/Synchronization Issues, Task Synchronization Techniques, Device Drivers, How to Choose an RTOS. TEXT BOOKS: 1. Introduction to Embedded Systems - Shibu K.V, Mc Graw Hill. REFERENCE BOOKS: 1. Embedded Systems - Raj Kamal, TMH. 2. Embedded System Design - Frank Vahid, Tony Givargis, John Wiley. 3. Embedded Systems ­ Lyla, Pearson, 2013 4. An Embedded Software Primer - David E. Simon, Pearson Education.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) DEVICE MODELLING (Core Elective ­II) UNIT -I: Introduction to Semiconductor Physics: Review of Quantum Mechanics, Boltzman transport equation, Continuity equation, Poisson equation. Integrated Passive Devices: Types and Structures of resistors and capacitors in monoLithic Technology, Dependence of model parameters on structures UNIT -II: Integrated Diodes: Junction and Schottky diodes in monolithic technologies ­ Static and Dynamic behavior ­ Small and large signal models ­ SPICE models Integrated Bipolar Transistor: Types and structures in monolithic technologies ­ Basic model (Eber-Moll) ­ Gunmel - Poon modeldynamic model, Parasitic effects ­ SPICE model ­Parameter extraction UNIT -III: Integrated MOS Transistor: NMOS and PMOS transistor ­ Threshold voltage ­ Threshold voltage equations ­ MOS device equations ­ Basic DC equations second order effects ­ MOS models ­ small signal AC characteristics ­ MOS FET SPICE model level 1, 2, 3 and 4 UNIT -IV: VLSI Fabrication Techniques: An overview of wafer fabrication, wafer processing ­ Oxidation ­ Patterning ­ Diffusion ­ Ion Implantation ­ Deposition ­ Silicon gate nMOS process ­ CMOS processes ­ n-well- p-well- twin tub- Silicon on insulator ­ CMOS process enhancements ­ Interconnects circuit elements UNIT -V: Modeling of Hetero Junction Devices: Band gap Engineering, Band gap Offset at abrupt Hetero Junction, Modified current continuity equations, Hetero Junction bipolar transistors (HBTs), SiGe TEXT BOOKS: 1. Introduction to Semiconductor Materials and Devices ­ Tyagi M. S, 2008, John Wiley Student Edition. 2. Solid State Circuits ­ Ben G. Streetman, Prentice Hall, 1997 REFERENCE BOOKS: 1. Physics of Semiconductor Devices ­ Sze S. M, 2nd Edition, Mcgraw Hill, New York, 1981. 2. Introduction to Device Modeling and Circuit Simulation ­ Tor A. Fijedly, Wiley-Interscience, 1997. 3. Introduction to VLSI Systems: A Logic, Circuit and System Perspective ­ Ming-BO Lin, CRC Press, 2011
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) SOFT COMPUTING TECHNIQUES (Open Elective - I) UNIT ­ I: Fundamentals of Neural Networks & Feed Forward Networks Basic Concept of Neural Networks, Human Brain, Models of an Artificial Neuron, Learning Methods, Neural Networks Architectures, Signal Layer Feed Forward Neural Network :The Perceptron Model, Multilayer Feed Forward Neural Network :Architecture of a Back Propagation Network(BPN), The Solution, Backpropagation Learning, Selection of various Parameters in BPN. Application of Back propagation Networks in Pattern Recognition & Image Processing. UNIT ­ II: Associative Memories & ART Neural Networks Basic concepts of Linear Associator, Basic concepts of Dynamical systems, Mathematical Foundation of Discrete-Time Hop field Networks(HPF), Mathematical Foundation of Gradient-Type Hopfield Networks, Transient response of Continuous Time Networks, Applications of HPF in Solution of Optimization Problem: Minimization of the Traveling salesman tour length, Summing networks with digital outputs, Solving Simultaneous Linear Equations, Bidirectional Associative Memory Networks; Cluster Structure, Vector Quantization, Classical Art Networks, Simplified ART Architecture. UNIT ­ III: fuzzy logic & Systems Fuzzy sets, Crisp Relations, Fuzzy Relations, Crisp Logic, Predicate Logic, Fuzzy Logic, Fuzzy Rule based system, Defuzzification Methods, Applications: Greg Viot's Fuzzy Cruise Controller, Air Conditioner Controller. UNIT ­ IV: Genetic Algorithms Basic Concepts of Genetic Algorithms (GA), Biological background, Creation of Offsprings, Working Principle, Encoding, Fitness Function, Reproduction, Inheritance Operators, Cross Over, Inversion and Deletion, Mutation Operator, Bit-wise Operators used in GA, Generational Cycle, Convergence of Genetic Algorithm. UNIT ­ V: Hybrid Systems Types of Hybrid Systems, Neural Networks, Fuzzy Logic, and Genetic Algorithms Hybrid, Genetic Algorithm based BPN: GA Based weight Determination, Fuzzy Back Propagation Networks: LR-type fuzzy numbers, Fuzzy Neuron, Fuzzy BP Architecture, Learning in Fuzzy BPN, Inference by fuzzy BPN. TEXT BOOKS: 1. Introduction to Artificial Neural Systems - J.M.Zurada, Jaico Publishers 2. Neural Networks, Fuzzy Logic & Genetic Algorithms: Synthesis & Applications -S.Rajasekaran, G.A. Vijayalakshmi Pai, July 2011, PHI, New Delhi. 3. Genetic Algorithms by David E. Gold Berg, Pearson Education India, 2006. 4. Neural Networks & Fuzzy Sytems- Kosko.B., PHI, Delhi,1994. REFERENCE BOOKS: 1. Artificial Neural Networks - Dr. B. Yagananarayana, 1999, PHI, New Delhi. 2. An introduction to Genetic Algorithms - Mitchell Melanie, MIT Press, 1998 3. Fuzzy Sets, Uncertainty and Information- Klir G.J. & Folger. T. A., PHI, Delhi, 1993.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. VLSI Design) IMAGE AND VIDEO PROCESSING (OPEN ELECTIVE-I) UNIT ­I: Fundamentals of Image Processing and Image Transforms: Basic steps of Image Processing System Sampling and Quantization of an image, Basic relationship between pixels. Image Segmentation: Segmentation concepts, Point, Line and Edge Detection, Thresholding, Region based segmentation. UNIT ­II: Image Enhancement: spatial domain methods: Histogram processing, Fundamentals of Spatial filtering, Smoothing spatial filters, Sharpening spatial filters. Frequency domain methods: Basics of filtering in frequency domain, Image smoothing, Image sharpening, Selective filtering. UNIT ­III: Image Compression: Image compression fundamentals - Coding Redundancy, Spatial and Temporal redundancy, Compression models: Lossy & Lossless, Huffman coding, Bit plane coding, Transform coding, Predictive coding, Wavelet coding, Lossy Predictive coding, JPEG Standards. UNIT -IV: Basic Steps of Video Processing: Analog Video, Digital Video. Time-Varying Image Formation models: Three-Dimensional Motion Models, Geometric Image Formation, Photometric Image Formation, Sampling of Video signals, Filtering operations. UNIT ­V: 2-D Motion Estimation: Optical flow, General Methodologies, Pixel Based Motion Estimation, BlockMatching Algorithm, Mesh based Motion Estimation, Global Motion Estimation, Region based Motion Estimation, Multi resolution motion estimation, Waveform based coding, Block based transform coding, Predictive coding, Application of motion estimation in Video coding. TEXT BOOKS: 1. Digital Image Processing ­ Gonzaleze and Woods, 3rd Ed., Pearson. 2. Video Processing and Communication ­ Yao Wang, Joem Ostermann and Ya­quin Zhang. 1st Ed., PH Int. REFRENCE BOOKS: 1. Digital Image Processing using MATLAB­ Gonzaleze and Woods, 2nd ed., Mc Graw Hill Education, 2010 2. Image Processing Analysis , and Machine Vision- Milan Sonka, Vaclan Hlavac, 3 ed., CENGAGE, 2008 3. Digital Video Processing ­ A Murat Tekalp, PERSON, 2010 4. Digital Image Processing ­ S.Jayaraman, S.Esakkirajan, T.Veera Kumar ­TMH, 2009
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) SOFTWARE DEFINED RADIO (Open Elective-I) UNIT -I: Introduction: The Need for Software Radios, What is Software Radio, Characteristics and benefits of software radio- Design Principles of Software Radio, RF Implementation issues- The Purpose of RF Front ­ End, Dynamic Range- The Principal Challenge of Receiver Design ­ RF Receiver FrontEnd Topologies- Enhanced Flexibility of the RF Chain with Software Radios- Importance of the Components to Overall Performance- Transmitter Architectures and Their Issues- Noise and Distortion in the RF Chain, ADC and DAC Distortion. UNIT -II: Profile and Radio resource management : Communication Profiles- Introduction, Communication Profiles, Terminal Profile, Service Profile , Network Profile, User Profile, Communication Profile Architecture, Profile Data Structure, XML Structure, Distribution of Profile Data, Access to Profile Data, Management of Communication Profiles, Communication Classmarks, Dynamic Classmarks for Reconfigurable Terminals, Compression and Coding, Meta Profile Data UNIT -III: Radio Resource Management in Heterogeneous Networks Introduction, Definition of Radio Resource Management, Radio Resource Units over RRM Phases, RRM Challenges and Approaches, RRM Modelling and Investigation Approaches, Investigations of JRRM in Heterogeneous Networks, Measuring Gain in the Upper Bound Due to JRRM, CircuitSwitched System, Packet-Switched System, Functions and Principles of JRRM, General Architecture of JRRM, Detailed RRM Functions in Sub-Networks and Overall Systems UNIT -IV: Reconfiguration of the Network Elements : Introduction, Reconfiguration of Base Stations and Mobile Terminals, Abstract Modelling of Reconfigurable Devices, the Role of Local Intelligence in Reconfiguration, Performance Issues, Classification and Rating of Reconfigurable Hardware, Processing Elements, Connection Elements, Global Interconnect Networks, Hierarchical Interconnect Networks, Installing a New Configuration, Applying Reconfiguration Strategies, Reconfiguration Based on Comparison, Resource Recycling, Flexible Workload Management at the Physical Layer, Optimised Reconfiguration, Optimisation Parameters and Algorithms, Optimization Algorithms, Specific Reconfiguration Requirements, Reconfiguring Base Stations, Reconfiguring Mobile Terminals UNIT -V: Object ­ Oriented Representation of Radios and Network Resources: Networks- Object Oriented Programming- Object Brokers- Mobile Application Environments- Joint Tactical Radio System. Case Studies in Software Radio Design: Introduction and Historical Perspective, SPEAK easyJTRS, Wireless Information Transfer System, SDR-3000 Digital Transceiver Subsystem, Spectrum Ware, CHARIOT. TEXT BOOKS: 1. Software Defined Radio Architecture System and Functions- Markus Dillinger, Kambiz Madani, WILEY 2003 2. Software Defined Radio: Enabling Technologies- Walter Tuttle Bee, 2002, Wiley Publications. REFERENCE BOOKS: 1. Software Radio: A Modern Approach to Radio Engineering - Jeffrey H. Reed, 2002, PEA Publication. 2. Software Defined Radio for 3G - Paul Burns, 2002, Artech House. 3. Software Defined Radio: Architectures, Systems and Functions - Markus Dillinger, Kambiz Madani, Nancy Alonistioti, 2003, Wiley. 4. Software Radio Architecture: Object Oriented Approaches to wireless System Enginering ­ Joseph Mitola, III, 2000, John Wiley & Sons.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­ I Sem. (VLSI Design) VLSI LABORATORY ­ I Note: Minimum of 10 programs from Part ­I and 2 programs from Part -II are to be conducted. Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification. Part ­I: VLSI Front End Design programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry Look Ahead Adder. 3. Design of 2-to-4 decoder 4. Design of 8-to-3 encoder (without and with parity) 5. Design of 8-to-1 multiplexer 6. Design of 4 bit binary to gray converter 7. Design of Multiplexer/ Demultiplexer, comparator 8. Design of Full adder using 3 modeling styles 9. Design of flip flops: SR, D, JK, T 10. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter 11. Design of a N- bit Register of Serial- in Serial ­out, Serial in parallel out, Parallel in Serial out and Parallel in Parallel Out. 12. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines). 13. Design of 4- Bit Multiplier, Divider. 14. Design of ALU to Perform ­ ADD, SUB, AND-OR, 1's and 2's Compliment, Multiplication, and Division. 15. Design of Finite State Machine. 16. Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits .
Part ­II: VLSI Back End Design programs: Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design/Transistor-level design/Hierarchical design/Verilog HDL or VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects (temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS). 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: Basic gates inverter CMOS NOR/ NAND gates CMOS XOR and MUX gates CMOS 1-bit full adder Static / Dynamic logic circuit (register cell) Latch Pass transistor Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) LOW POWER VLSI DESIGN UNIT ­I: Fundamentals: Need for Low Power Circuit Design, Sources of Power Dissipation ­ Switching Power Dissipation, Short Circuit Power Dissipation, Leakage Power Dissipation, Glitching Power Dissipation, Short Channel Effects ­Drain Induced Barrier Lowering and Punch Through, Surface Scattering, Velocity Saturation, Impact Ionization, Hot Electron Effect. UNIT ­II: Low-Power Design Approaches: Low-Power Design through Voltage Scaling ­ VTCMOS circuits, MTCMOS circuits, Architectural Level Approach ­Pipelining and Parallel Processing Approaches. Switched Capacitance Minimization Approaches: System Level Measures, Circuit Level Measures, Mask level Measures. UNIT ­III: Low-Voltage Low-Power Adders: Introduction, Standard Adder Cells, CMOS Adder's Architectures ­ Ripple Carry Adders, Carry Look-Ahead Adders, Carry Select Adders, Carry Save Adders, Low-Voltage Low-Power Design Techniques ­Trends of Technology and Power Supply Voltage, Low-Voltage Low-Power Logic Styles. UNIT ­IV: Low-Voltage Low-Power Multipliers: Introduction, Overview of Multiplication, Types of Multiplier Architectures, Braun Multiplier, Baugh-Wooley Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier. UNIT ­V: Low-Voltage Low-Power Memories: Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM, Memory Cell, Precharge and Equalization Circuit, Low-Power SRAM Technologies, Basics of DRAM, SelfRefresh Circuit, Future Trend and Development of DRAM. TEXT BOOKS: 1. CMOS Digital Integrated Circuits ­ Analysis and Design ­ Sung-Mo Kang, Yusuf Leblebici, TMH, 2011. 2. Low-Voltage, Low-Power VLSI Subsystems ­ Kiat-Seng Yeo, Kaushik Roy, TMH Professional Engineering. REFERENCE BOOKS: 1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective ­ Ming-BO Lin, CRC Press, 2011 2. Low Power CMOS Design ­ AnanthaChandrakasan, IEEE Press/Wiley International, 1998. 3. Low Power CMOS VLSI Circuit Design ­ Kaushik Roy, Sharat C. Prasad, John Wiley & Sons, 2000. 4. Practical Low Power Digital VLSI Design ­ Gary K. Yeap, Kluwer Academic Press, 2002. 5. Low Power CMOS VLSI Circuit Design ­ A. Bellamour, M. I. Elamasri, Kluwer Academic Press, 1995. 6. Leakage in Nanometer CMOS Technologies ­ Siva G. Narendran, AnathaChandrakasan, Springer, 2005.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) DESIGN FOR TESTABILITY UNIT -I: Introduction to Testing: Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends affecting Testing, Types of Testing, Fault Modeling: Defects, Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models, Single Stuck-at Fault. UNIT -II: Logic and Fault Simulation: Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms for Truevalue Simulation, Algorithms for Fault Simulation, ATPG. UNIT -III: Testability Measures: SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan Design: AdHoc DFT Methods, Scan Design, Partial-Scan Design, Variations of Scan. UNIT -IV: Built-In Self-Test: The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation, Response Compaction, Built-In Logic Block Observers, Test-Per-Clock, Test-Per-Scan BIST Systems, Circular Self Test Path System, Memory BIST, Delay Fault BIST. UNIT -V: Boundary Scan Standard: Motivation, System Configuration with Boundary Scan: TAP Controller and Port, Boundary Scan Test Instructions, Pin Constraints of the Standard, Boundary Scan Description Language: BDSL Description Components, Pin Descriptions. TEXT BOOKS: 1. Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits - M.L. Bushnell, V. D. Agrawal, Kluwer Academic Pulishers. REFERENCE BOOKS: 1. Digital Systems and Testable Design - M. Abramovici, M.A.Breuer and A.D Friedman, Jaico Publishing House. 2. Digital Circuits Testing and Testability - P.K. Lala, Academic Press.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) CMOS MIXED SIGNAL CIRCUIT DESIGN UNIT -I: Switched Capacitor Circuits: Introduction to Switched Capacitor circuits- basic building blocks, Operation and Analysis, Non-ideal effects in switched capacitor circuits, Switched capacitor integrators first order filters, Switch sharing, biquad filters. UNIT -II: Phased Lock Loop (PLL): Basic PLL topology, Dynamics of simple PLL, Charge pump PLLs-Lock acquisition, Phase/Frequency detector and charge pump, Basic charge pump PLL, Non-ideal effects in PLLs-PFD/CP non-idealities, Jitter in PLLs, Delay locked loops, applications UNIT -III: Data Converter Fundamentals: DC and dynamic specifications, Quantization noise, Nyquist rate D/A converters- Decoder based converters, Binary-Scaled converters, Thermometer-code converters, Hybrid converters UNIT -IV: Nyquist Rate A/D Converters: Successive approximation converters, Flash converter, Two-step A/D converters, Interpolating A/D converters, Folding A/D converters, Pipelined A/D converters, Time-interleaved converters. UNIT -V: Oversampling Converters: Noise shaping modulators, Decimating filters and interpolating filters, Higher order modulators, Delta sigma modulators with multibit quantizers, Delta sigma D/A TEXT BOOKS: 1. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition, 2002 2. CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University Press, International Second Edition/Indian Edition, 2010. 3. Analog Integrated Circuit Design- David A. Johns,Ken Martin, Wiley Student Edition, 2013 REFERENCE BOOKS: 1. CMOS Integrated Analog-to- Digital and Digital-to-Analog converters-Rudy Van De Plassche, Kluwer Academic Publishers, 2003 2. Understanding Delta-Sigma Data converters-Richard Schreier, Wiley Interscience, 2005. 3. CMOS Mixed-Signal Circuit Design - R. Jacob Baker, Wiley Interscience, 2009.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES (ELECTIVE -III) UNIT ­I: Introduction to Digital Signal Processing: Introduction, a Digital signal-processing system, the sampling process, discrete time sequences. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear time-invariant systems, Digital filters, Decimation and interpolation. Computational Accuracy in DSP Implementations: Number formats for signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP implementations, A/D Conversion errors, DSP Computational errors, D/A Conversion Errors, Compensating filter. UNIT ­II: Architectures for Programmable DSP Devices: Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation UNIT, Programmability and program execution, Speed Issues, Features for External interfacing. UNIT -III: Programmable Digital Signal Processors: Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX Processors, Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX Instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C54XX Processors, Pipeline Operation of TMS320C54XX Processors. UNIT ­IV: analog devices Family of DSP Devices: Analog Devices Family of DSP Devices ­ ALU and MAC block diagram, Shifter Instruction, Base Architecture of ADSP 2100, ADSP-2181 high performance Processor. Introduction to Black fin Processor - The Black fin Processor, Introduction to Micro Signal Architecture, Overview of Hardware Processing Units and Register files, Address Arithmetic Unit, Control Unit, Bus Architecture and Memory, Basic Peripherals. UNIT ­V: Interfacing Memory and I/O Peripherals to Programmable DSP Devices: Memory space organization, External bus interfacing signals, Memory interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA). TEXT BOOKS: 1. Digital Signal Processing ­ Avtar Singh and S. Srinivasan, Thomson Publications, 2004. 2. A Practical Approach To Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran, Ananthi. S, New Age International, 2006/2009 3. Embedded Signal Processing with the Micro Signal Architecture: Woon-Seng Gan, Sen M. Kuo, Wiley- IEEE Press, 2007 REFERENCE BOOKS: 1. Digital Signal Processors, Architecture, Programming and Applications ­ B. Venkataramani and M. Bhaskar, 2002, TMH. 2. Digital Signal Processing ­ Jonatham Stein, 2005, John Wiley. 3. DSP Processor Fundamentals, Architectures & Features ­ Lapsley et al. 2000, S. Chand & Co. 4. Digital Signal Processing Applications Using the ADSP-2100 Family by The Applications Engineering Staff of Analog Devices, DSP Division, Edited by Amy Mar, PHI 5. The Scientist and Engineer's Guide to Digital Signal Processing by Steven W. Smith, Ph.D., California Technical Publishing, ISBN 0-9660176-3-3, 1997 6. Embedded Media Processing by David J. Katz and Rick Gentile of Analog Devices, Newnes , ISBN 0750679123, 2005.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS)
M. Tech ­ I Year ­I I Sem. (VLSI Design)
ASIC DESIGN
UNIT I ASIC DESIGN STYLES: Introduction ­ categories-Gate arrays-Standard cells-Cell based ASICs-Mixed mode and analogue ASICs ­ PLDs.
ASICS ­ PROGRAMMABLE LOGIC DEVICES: Overview ­ PAL ­based PLDs: Structures; PAL Characteristics ­ FPGAs: Intoduction, selected families ­ design outline. UNIT II ASICS ­DESIGN ISSUES: Design methodologies and design tools ­ design for testability ­ economies.
ACISS CHARACTERISTICS AND PERFORMANCE: design styles, gate arrays, standard cell -based ASICs, Mixed mode and analogue ASICs.
UNIT III ASICS-DESIGN TECHNIQUES: Overview- Design flow and methodology-Hardware description languagessimulation and checking-commercial design tools- FPGA Design tools: XILINX, ALTERA UNIT IV LOGIC SYNTHESIS, SIMULATION AND TESTING: Verilog and logic synthesis -VHDL and logic synthesis types of simulation -boundary scan test - fault simulation- automatic test pattern generation.
ASIC CONSTRUCTION: Floor planning, placement and routing system partition.
UNIT V FPGA PARTITIONING: Partitioning Methods-Floor Planning- Placement-Physical Design Flow-Global Routing-Detailed Routing ­Special Routing-Circuit Extraction-DRC.
TEXT BOOKS: 1. L.J.Herbst,"Integrated circuit engineering", OXFORD SCIENCE Publications, 1996. REFERENCES: 1. M.J.S.Smith, "Application - Specific integrated circuits", Addison-Wesley Longman Inc 1997.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) HARDWARE DESCRIPTION LANGUAGES UNIT I HARDWARE MODELING WITH THE VERILOG HDL : Hardware Encapsulation -The Verilog Module, Hardware Modeling Verilog Primitives, Descriptive Styles, Structural Connections, Behavioral Description In Verilog, Hierarchical Descriptions of Hardware, Structured (Top Down) Design Methodology, Arrays of Instances, Using Verilog for Synthesis, Language Conventions, Representation of Numbers. LOGIC SYSTEM, DATA TYPES AND OPERATORS FOR MODELING IN VERILOG HDL: User-Defined Primitives, User Defined Primitives ­ Combinational Behavior User-Defined Primitives ­Sequential Behavior, Initialization of Sequential Primitives. Verilog Variables, Logic Value Set, Data Types, Strings. Constants, Operators, Expressions and Operands, Operator Precedence Models Of Propagation Delay; Built-In Constructs for Delay, Signal Transitions, Verilog Models for Gate Propagation Delay (Inertial Delay), Time Scales for Simulation, Verilog Models for Net Delay (Transport Delay), Module Paths and Delays, Path Delays and Simulation, Inertial Delay Effects and Pulse Rejection. UNIT II BEHAVIORAL DESCRIPTIONS IN VERILOG HDL: Verilog Behaviors, Behavioral Statements, Procedural Assignment, Procedural Continuous Assignments, Procedural Timing Controls and Synchronization, IntraAssignment, Delay-Blocked Assignments, Non-Blocking Assignment, Intra-Assignment Delay: Non-Blocking Assignment, Simulation of Simultaneous Procedural Assignments, Repeated Intra Assignment Delay,
Indeterminate Assignments and Ambiguity, Constructs for Activity Flow Control, Tasks and Functions, Summary of Delay Constructs in Verilog, System Tasks for Timing Checks, Variable Scope Revisited, Module Contents, Behavioral Models of Finite State Machines. UNIT-III SYNTHESIS OF COMBINATIONAL LOGIC: HDL-Based Synthesis, Technology-Independent Design, Benefits of Synthesis, Synthesis Methodology, Vendor Support, Styles for Synthesis of Combinational Logic, Technology Mapping and Shared Resources, Three State Buffers, Three State Outputs and Don't Cares, Synthesis of Sequential Logic Synthesis of Sequential Udps, Synthesis of Latches, Synthesis of EdgeTriggered Flip Flops, Registered Combinational Logic, Shift Registers and Counters, Synthesis of Finite State Machines, Resets, Synthesis of Gated Clocks, Design Partitions and Hierarchical Structures. UNIT IV SYNTHESIS OF LANGUAGE CONSTRUCTS: Synthesis of Nets, Synthesis of Register Variables, Restrictions on Synthesis of "X" and "Z", Synthesis of Expressions and Operators, Synthesis of Assignments, Synthesis of Case and Conditional Statement, Synthesis of Resets, Timings Controls in Synthesis, Synthesis of Multi-Cycle Operations, Synthesis of Loops, Synthesis if Fork Join Blocks, Synthesis of The Disable Statement Synthesis of User-Defined Tasks, Synthesis of User-Defined Functions, Synthesis of Specify Blocks, Synthesis of Compiler Directives. UNIT V SWITCH-LEVEL MODELS IN VERILOG: MOS Transistor Technology, Switch Level Models of MOS Transistors, Switch Level Models of Static CMOS Circuits, Alternative Loads and Pull Gates, CMOS Transmission Gates. Bio-Directional Gates (Switches), Signal Strengths, Ambiguous Signals, Strength Reduction By Primitives, Combination and Resolution of Signal Strengths, Signal Strengths and Wired Logic. Design Examples in Verilog. Text Books : 5. M.D.CILETTI, "Modeling, Synthesis and Rapid Prototyping with the Verilog HDL", Prentice-Hall, 1999. 6. Z.NAWABI, "VHDL Analysis and Modeling of Digital Systems", (2/E), McGraw Hill, 1998. REFERENCES: 5. M.G.ARNOLD, "Verilog Digital ­ Computer Design", Prentice-Hall (PTR), 1999. 6. PERRY, "VHDL", (3/E), McGraw Hill.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) OPTIMIZATION TECHNIQUES IN VLSI DESIGN (CORE ELECTIVE -IV) UNIT ­I: Statistical Modeling: Modeling sources of variations, Monte Carlo techniques, Process variation modeling- Pelgrom s model, Principle component based modeling, Quad tree based modeling, Performance modeling-Response surface methodology, delay modeling, interconnect delay models. UNIT ­II: Statistical Performance, Power and Yield Analysis Statistical timing analysis, parameter space techniques, Bayesian networks Leakage models, High level statistical analysis, Gate level statistical analysis, dynamic power, leakage power, temperature and power supply variations, High level yield estimation and gate level yield estimation. UNIT ­III: Convex Optimization: Convex sets, convex functions, geometric programming, trade-off and sensitivity analysis, Generalized geometric programming, geometric programming applied to digital circuit gate sizing, Floor planning, wire sizing, Approximation and fitting- Monomial fitting, Maxmonomial fitting, Posynomial fitting. UNIT ­IV: Genetic Algorithm: Introduction, GA Technology-Steady State Algorithm-Fitness Scaling-Inversion GA for VLSI Design, Layout and Test automation- partitioning-automatic placement, routing technology, Mapping for FPGA- Automatic test generation- Partitioning algorithm Taxonomy-Multi-way Partitioning Hybrid genetic-encoding-local improvement-WDFR Comparison of CAS-Standard cell placement-GASP algorithm-unified algorithm. UNIT ­V: GA Routing Procedures and Power Estimation: Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame work-test generation procedures, Power estimation-application of GA-Standard cell placement-GA for ATG-problem encodingfitness function-GA Vs Conventional algorithm. TEXT BOOKS / REFERENCE BOOKS: 1. Statistical Analysis and Optimization for VLSI: Timing and Power - Ashish Srivastava, Dennis Sylvester, David Blaauw, Springer, 2005. 2. Genetic Algorithm for VLSI Design, Layout and Test Automation - Pinaki Mazumder, E.Mrudnick, Prentice Hall,1998. 3. Convex Optimization - Stephen Boyd, Lieven Vandenberghe, Cambridge University Press, 2004.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) SYSTEM ON CHIP ARCHITECTURE (CORE ELECTIVE -IV) UNIT ­I: Introduction to the System Approach: system architecture, Components of the system, Hardware & Software, Processor Architectures, Memory and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity. UNIT ­II: Processors: Introduction , Processor Selection for SOC, Basic concepts in Processor Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors. UNIT ­III: Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split ­ I, and D ­ Caches, Multilevel Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor ­ memory interaction. UNIT -IV: Interconnect Customization and Configuration: Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization: An overview, Customizing Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable devices, InstanceSpecific design, Customizable Soft Processor, Reconfiguration - overhead analysis and trade-off analysis on reconfigurable Parallelism. UNIT ­V: Application Studies / Case Studies: SOC Design approach, AES algorithms, Design and evaluation, Image compression ­ JPEG compression. TEXT BOOKS: 1. computer system Design System-on-Chip - Michael J. Flynn and Wayne Luk, Wiely India Pvt. Ltd. 2. ARM System on Chip Architecture ­ Steve Furber ­2nd Ed., 2000, Addison Wesley Professional. REFERENCE BOOKS: 1. Design of System on a Chip: Devices and Components ­ Ricardo Reis, 1st Ed., 2004, Springer 2. Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology) ­ Jason Andrews ­ Newnes, BK and CDROM. 3. System on Chip Verification ­ Methodologies and Techniques ­Prakash Rashinkar, Peter Paterson and Leena Singh L, 2001, Kluwer Academic Publishers.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) SEMICONDUCTOR MEMORY DESIGN AND TESTING (CORE ELECTIVE -IV) UNIT -I: Random Access Memory Technologies: SRAM ­ SRAM cell structures, MOS SRAM Architecture, MOS SRAM cell and peripheral circuit operation, Bipolar SRAM technologies, SOI technology, Advanced SRAM architectures and technologies, Application specific SRAMs, DRAM ­ DRAM technology development, CMOS DRAM, DRAM cell theory and advanced cell structures, BICMOS DRAM, soft error failure in DRAM, Advanced DRAM design and architecture, Application specific DRAM UNIT -II: Non-volatile Memories: Masked ROMs, High density ROM, PROM, Bipolar ROM, CMOS PROMS, EPROM, Floating gate EPROM cell, One time programmable EPROM, EEPROM, EEPROM technology and architecture, Non-volatile SRAM, Flash Memories (EPROM or EEPROM), advanced Flash memory architecture UNIT -III: Memory Fault Modeling Testing and Memory Design for Testability and Fault Tolerance: RAM fault modeling, Electrical testing, Pseudo Random testing, Megabit DRAM Testing, non-volatile memory modeling and testing, IDDQ fault modeling and testing, Application specific memory testing, RAM fault modeling, BIST techniques for memory UNIT -IV: Semiconductor Memory Reliability and Radiation Effects: General reliability issues RAM failure modes and mechanism, Non-volatile memory reliability, reliability modeling and failure rate prediction, Design for Reliability, Reliability Test Structures, Reliability Screening and qualification, Radiation effects, Single Event Phenomenon (SEP), Radiation Hardening techniques, Radiation Hardening Process and Design Issues, Radiation Hardened Memory characteristics, Radiation Hardness Assurance and Testing, Radiation Dosimetry, Water Level Radiation Testing and Test structures UNIT -V: Advanced Memory Technologies and High-density Memory Packing Technologies: Ferroelectric RAMs (FRAMs), GaAs FRAMs, Analog memories, magneto resistive RAMs (MRAMs), Experimental memory devices, Memory Hybrids and MCMs (2D), Memory Stacks and MCMs (3D), Memory MCM testing and reliability issues, Memory cards, High Density Memory Packaging Future Directions TEXT BOOKS: 1. Semiconductor Memories Technology ­ Ashok K. Sharma, 2002, Wiley. 2. Advanced Semiconductor Memories ­ Architecture, Design and Applications - Ashok K. Sharma- 2002, Wiley. 3. Modern Semiconductor Devices for Integrated Circuits ­ Chenming C Hu, 1st Ed., Prentice Hall.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) SCRIPTING LANGUAGES (OPEN ELECTIVE -II) UNIT -I: Introduction to Scripts and Scripting: Characteristics and uses of scripting languages, Introduction to PERL, Names and values, Variables and assignment, Scalar expressions, Control structures, Built-in functions, Collections of Data, Working with arrays, Lists and hashes, Simple input and output, Strings, Patterns and regular expressions, Subroutines, Scripts with arguments. UNIT -II: Advanced PERL: Finer points of Looping, Subroutines, Using Pack and Unpack, Working with files, Navigating the file system, Type globs, Eval, References, Data structures, Packages, Libraries and modules, Objects, Objects and modules in action, Tied variables, Interfacing to the operating systems, Security issues. UNIT -III: TCL: The TCL phenomena, Philosophy, Structure, Syntax, Parser, Variables and data in TCL, Control flow, Data structures, Simple input/output, Procedures, Working with Strings, Patterns, Files and Pipes, Example code. UNIT -IV: Advanced TCL: The eval, source, exec and up-level commands, Libraries and packages, Namespaces, Trapping errors, Eventdriven programs, Making applications 'Internet-aware', 'Nuts-and-bolts' internet programming, Security issues, running untrusted code, The C interface. UNIT -V: TK and JavaScript: Visual tool kits, Fundamental concepts of TK, TK by example, Events and bindings, Geometry managers, PERL-TK. JavaScript ­ Object models, Design Philosophy, Versions of JavaScript, The Java Script core language, Basic concepts of Pythan. Object Oriented Programming Concepts (Qualitative Concepts Only): Objects, Classes, Encapsulation, Data Hierarchy. TEXT BOOKS: 1. The World of Scripting Languages- David Barron, Wiley Student Edition, 2010. 2. Practical Programming in Tcl and Tk - Brent Welch, Ken Jones and Jeff Hobbs., Fourth edition. 3. Java the Complete Reference - Herbert Schildt, 7th Edition, TMH. REFERENCE BOOKS: 1. Tcl/Tk: A Developer's Guide- Clif Flynt, 2003, Morgan Kaufmann SerieS. 2. Tcl and the Tk Toolkit- John Ousterhout, 2nd Edition, 2009, Kindel Edition. 3. Tcl 8.5 Network Programming book- Wojciech Kocjan and Piotr Beltowski, Packt Publishing. 4. Tcl/Tk 8.5 Programming Cookbook- Bert Wheeler
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) CODING THEORY AND TECHNIQUES UNIT -I: Coding for Reliable Digital Transmission and Storage: Mathematical model of Information, A Logarithmic Measure of Information, Average and Mutual Information and Entropy, Types of Errors, Error Control Strategies. Linear Block Codes: Introduction to Linear Block Codes, Syndrome and Error Detection, Minimum Distance of a Block code, Error-Detecting and Error-correcting Capabilities of a Block code, Standard array and Syndrome Decoding, Probability of an undetected error for Linear Codes over a BSC, Hamming Codes. Applications of Block codes for Error control in data storage system UNIT ­II: Cyclic Codes: Description, Generator and Parity-check Matrices, Encoding, Syndrome Computation and Error Detection, Decoding ,Cyclic Hamming Codes, Shortened cyclic codes, Error-trapping decoding for cyclic codes, Majority logic decoding for cyclic codes. UNIT ­III: Convolutional Codes: Encoding of Convolutional Codes, Structural and Distance Properties, maximum likelihood decoding, Sequential decoding, Majority- logic decoding of Convolution codes. Application of Viterbi Decoding and Sequential Decoding, Applications of Convolutional codes in ARQ system. UNIT ­IV: Burst ­Error-Correcting Codes: Decoding of Single-Burst error Correcting Cyclic codes, Single-Burst-ErrorCorrecting Cyclic codes, Burst-Error-Correcting Convolutional Codes, Bounds on Burst Error-Correcting Capability, Interleaved Cyclic and Convolutional Codes, Phased-Burst ­Error-Correcting Cyclic and Convolutional codes. UNIT -V: BCH ­ Codes: BCH code- Definition, Minimum distance and BCH Bounds, Decoding Procedure for BCH Codes- Syndrome Computation and Iterative Algorithms, Error Location Polynomials and Numbers for single and double error correction TEXT BOOKS: 1. Error Control Coding- Fundamentals and Applications ­Shu Lin, Daniel J.Costello,Jr, Prentice Hall, Inc. 2. Error Correcting Coding Theory-Man Young Rhee- 1989, McGraw-Hill Publishing. REFERENCE BOOKS: 1. Digital Communications-Fundamental and Application - Bernard Sklar, PE. 2. Digital Communications- John G. Proakis, 5th Ed., 2008, TMH. 3. Introduction to Error Control Codes-Salvatore Gravano-Oxford 4. Error Correction Coding ­ Mathematical Methods and Algorithms ­ Todd K.Moon, 2006, Wiley India. 5. information theory, Coding and Cryptography ­ Ranjan Bose, 2nd Edition, 2009, TMH.
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) ADHOC AND WIRELESS sensor networkS (OPEN ELECTIVE ­ II) UNIT-I: Wireless LANS and PANS: Introduction, Fundamentals of WLANS, IEEE 802.11 Standard, HIPERLAN Standard, Bluetooth, Home RF. Wireless Internet: Wireless Internet, Mobile IP, TCP in Wireless Domain, WAP, Optimizing Web Over Wireless. UNIT-II: AD HOC Wireless Networks: Introduction, Issues in Ad Hoc Wireless Networks, AD Hoc Wireless Internet. MAC Protocols for Ad Hoc Wireless Networks: Introduction, Issues in Designing a MAC protocol for Ad Hoc Wireless Networks, Design goals of a MAC Protocol for Ad Hoc Wireless Networks, Classifications of MAC Protocols, Contention - Based Protocols, Contention - Based Protocols with reservation Mechanisms, Contention ­ Based MAC Protocols with Scheduling Mechanisms, MAC Protocols that use Directional Antennas, Other MAC Protocols. UNIT -III: Routing Protocols: Introduction, Issues in Designing a Routing Protocol for Ad Hoc Wireless Networks, Classification of Routing Protocols, Table ­Driven Routing Protocols, On ­ Demand Routing Protocols, Hybrid Routing Protocols, Routing Protocols with Efficient Flooding Mechanisms, Hierarchical Routing Protocols, Power ­ Aware Routing Protocols. Transport Layer and Security Protocols: Introduction, Issues in Designing a Transport Layer Protocol for Ad Hoc Wireless Networks, Design Goals of a Transport Layer Protocol for Ad Hoc Wireless Networks, Classification of Transport Layer Solutions, TCP Over Ad Hoc Wireless Networks, Other Transport Layer Protocol for Ad Hoc Wireless Networks, Security in Ad Hoc Wireless Networks, Network Security Requirements, Issues and Challenges in Security Provisioning, Network Security Attacks, Key Management, Secure Routing in Ad Hoc Wireless Networks. UNIT ­IV: Quality of Service: Introduction, Issues and Challenges in Providing QoS in Ad Hoc Wireless Networks, Classification of QoS Solutions, MAC Layer Solutions, Network Layer Solutions, QoS Frameworks for Ad Hoc Wireless Networks. Energy Management: Introduction, Need for Energy Management in Ad Hoc Wireless Networks, Classification of Ad Hoc Wireless Networks, Battery Management Schemes, Transmission Power Management Schemes, System Power Management Schemes. UNIT ­V: Wireless Sensor Networks: Introduction, Sensor Network Architecture, Data Dissemination, Data Gathering, MAC Protocols for Sensor Networks, Location Discovery, Quality of a Sensor Network, Evolving Standards, Other Issues. TEXT BOOKS: 1. Ad Hoc Wireless Networks: Architectures and Protocols - C. Siva Ram Murthy and B.S.Manoj, 2004, PHI. 2. Wireless Ad- hoc and Sensor Networks: Protocols, Performance and Control - Jagannathan Sarangapani, CRC Press REFERENCE BOOKS: 1. Ad- Hoc Mobile Wireless Networks: Protocols & Systems, C.K. Toh ,1 ed. Pearson Education. 2. Wireless Sensor Networks - C. S. Raghavendra, Krishna M. Sivalingam, 2004, Springer
JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES (UGC-AUTONOMOUS) M. Tech ­ I Year ­I I Sem. (VLSI Design) VLSI LABORATORY - II Note: All the following digital/analog circuits are to be designed and implemented using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design/Transistor-level design/Hierarchical design/Verilog HDL or VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects (temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitic and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS). VLSI Back End Design programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: CMOS inverter CMOS NOR/ NAND gates CMOS XOR and MUX gates CMOS half adder and full adder Static / Dynamic logic circuits (register cell) Latch Pass transistor 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier 6. Analog Circuit simulation (AC analysis) ­ CS & CD amplifier 7. System level design using PLL.

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