Handbook of digital techniques for high-speed design, T Granberg

Tags: Exercises, Contents, Timing Models, Design Data Management, Mentor Graphics, Device Families, Design Reuse, Memory Technologies, Low Voltage Differential Signaling, Differential, Fiber Optics, Signal Integrity, Expedition PCB, Design Examples, FPGA Advantage, Design Process, Design Methodology, EMC Analysis, Pattern Test Circuit, Verification, Lowering Electromagnetic Interference, Electrical Board Description, Timing Methods, Expedition PCB AwoActive Technology Dynanuc Area, Chapter 22 Mentor Graphics, Design Example, Differential Signaling, Test Card, Eye Diagrams, Reference Design, Test Equipment, FCRAM, WarpLink, Electrical Optical Circuit Board PolyGuide Tppcat, Serializer, Speed Test, Random Data, Measurement Results, RLDRAM, Flash Memory, GTLP, Backplane Transceiver Logic, SSTL, Electrical Optical Circuit Board, Gunning Transceiver Logic, QDR, Double Data Rate, DDR SDRAM, IBIS, Flash, LVDS
Content: HANDBOOK OF DIGITAL TECHNIQUES FOR HIGH-SPEED DESIGN design examples, Signaling and Memory Technologies, fiber optics, Modeling and Simulation to Ensure Signal Integrity Tom Granberg, Ph.D .
Prentice Hall PTR
UPPER SADDLE RIVE NJ 07458
PRENTICE HALL
WWWIPHPTP.COM
PTR
CONTENTS
Preface How This Book Is Organized This Textbook Was Written with educational institutions in Mind University Courses for Which This Book Is Suitable Solutions Manual Is Available Cash for Identifying Textbook Errors How This Book Was Prepared Personal Acknowledgments Technical Acknowledgments Part -1 Introduction Chapter y Trends in High-Speed Design 1,1 Everything Keeps Getting Faster and Faster? 1.2 emerging technologies and Industry Trends 1 .2.1 Major Drivers of Printed circuit board (PCB) Technology 1 .2,2 Drivers of Innovation 1 .2.3 110 Signaling Standards 1 .2.4 Web Site as Retailer 1,2.5 Memories 1 .2.6 On-Die Terminations 1 .3 Trends in Bus Architecture 1 .3 .1 Moving from Parallel to Serial 1 .3 .2 The Power ofTools 1 .3 .3 ASSPs and ASMs 1 .4 High-Speed Design as an Offshoot from Microwave Theory 1 .5 Background Disciplines Needed for High-Speed Design 1 .5.1 High-Speed Conferences and Forums 1 .6 Book Organization 1.7 Exercises
xxxvii xxxvii xxxix xl xl xl x1i x1i xliii I 3 3 6 6 6 7 8 8 9 9 10 11 12 12 13 13 14 15
Chapter 2 ASICs, Backplane Configurations, and SerDes Technology 2.1 Application-Specific Integrated Circuits (ASICs) 2.2 Bus Configurations 2.2.1 Single-Termination Multidrop 2.2.2 Double-Termination Multidrop 2.2.3 Data Distribution with Point-to-Point Links 2.2.4 Muitipoint 2.2.5 Switch Matrix Mesh and Fabric Point-to-Point Bus Architeclures 2.3 SerDes Devices 2.3.1 SerDes Device Fundamentals 2.3.2 SerDes at 5 Gbps 2.3.3 SerDes Multibit Signal Encoding 2.4 Electrical Interconnects vs. Fiber Optics 2.5 Subtleties of Device Families 2.5.1 Logic vs, Interface Families 2 .5.2 Murky Device Categories 2 .5.3 Logic Family vs. Signaling Standard 2.6 EDN Magazine's Microprocessor Directory 2.7 Exercises Chapter 3 A Few Basics on Signal Integrity 3.1 transmission lines and Termination 3.1 .1 Transmission Line Equations 3 .1 .2 Reflection Coefficients, Lattice Diagrams, and Termination 3.2 Important High-Speed Concepts 3.2.1 Rise Time and Edge Rate 3.2.2 Length of the Rising Edge 3.2.3 Knee Frequency 3.2.4 Single-Ended vs. Differential Transmission 3.2.5 Fast Edge Rate Effects 3 .2.6 Parasitics 3.3 High-Frequency Effects : Skin Effect, Crowding Effect, Return Path Resistance, and Frequency-Dependent Dielectric Loss 3.4 Sitter Measurements Using Eye patterns 3.5 BER Testing 3.6 Exercises
Contents 17 17 18 18 19 19 20 20 21 21 21 24 26 26 27 27 28 28 28 29 3x . 31 31 34 38 38 39 40 40 41 42 42 43 46 47
Contents
Part 2 Signaling Technologies and Devices
49
Chapter 4 Gunning Transceiver Logic
(GTL, GTLP, GTL+, AGTL+)
51,
4.1 Evolution from Backplane Transceiver Logic (BTL)
51
4.2 Gunning Transceiver Logic (GTL)
53
4,3 Gunning Transceiver Logic Plus (GTLP)
54
4,3 .1 GTLP General Description and Applications
54
4.3.2 GTLP Throughput and Performance
56
4.3.3 GTLP Signaling Levels, Noise Margins, and Current Drive
56
4.3 .4 GTLP Device Features
58
Live Insertion and EStractioti
58
Controller) Edge Rates
SS
Busltoid (A Port)
60
4.3 .5 GTLP Backplane Design Considerations
61
4,3 .6 GTLP Power Consumption
64
4,4 Intel's AGTL+ and GTL+
65
4.5 GTLPIGTLIGTL+/AGTL+ Summary
67
4.6 Exercises
69
Chapter 5 Low Voltage Differential Signaling (LVDS)
71
5.1 Introduction to LVDS
71
5,1 .1 How LVDS Works
73
5.1 .2 Why Low Swing Differential?
77
5.1 .3 The LVDS and M-LVDS Standards
77
The TIAIEIA-644-A Standard
78
5.1 .4 Appearance of Laboratory LVDS Waveforms
80
More Discussion of the Evahiation Boairl
82
Conrnnon-Mode Noise
84
of Probing High-Speed LVDS Signals
86
5.1 .5 Easy Termination
87
5,1 .6 Maximum Switching Speed
88
5.1 .7 Saving Power
88
5.1 .8 LVDS Configurations
88
5.1.9 Low Voltage Differential Signaling (LVDS) Families
90
5,1 .10 LVDS as a Low-Cost Design Solution
91
5.1 .11 Example of the Wide Range of LVDS Solutions
92
A 5.2 Comparison of LVDS to Other Signaling Technologies Using Design Examples 5.2.1 LVDS Drivers and Receivers 5.2.2 100 Mbps Serial Interconnect 5.2.3 LVDS Channel Link Scrializers 5.2.4 1 Gbps 16-Bit Interconnect 5.2.5 1 .4 Gbps 56-Bit Backplane 5.3 Summary of LVDS Features and Applications 5 .4 Exercises Chapter 6 Bus LVDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS) 6.1 Justification for Enhanced Versions of LVDS 6.2 Bus LVDS (BLVDS) 6.2.1 System Benefits of Bus LVDS 6.2.2 High-Speed Capability 6.2.3 Low Power 6.2.4 Low Swing, Low Noise, and Low EMI 6.2.5 Low System Cost 6.2.6 Bus Failsafe Biasing 6.2.7 Hot Plugging (Live Insertion) 6.3 LVDS Multipoint (LVDM) 6.4 Multipoint LVDS (M-LVDS) 6.4.1 The TIAIEIA-899 Standard 6.5 Selecting BLVDS, BLVM, and M-LVDS Devices 6.6 Exercises Chapter 7 High-Speed Transceiver Logic (HSTL) and Stub-Series Terminated Logic (SSTL) 7.1 High-Speed Transceiver Logic (HSTL) 7.1 .1 The HSTL Standard 7.1 .2 Supply Voltages and Logic Levels 7.1 .3 Classes of HSTL Output Buffers 7.1 .4 FPGAs with HSTL 110s 7.1 .5 HSTL Summary 7 .2 Stub-Series Terminated Logic (SSTL) 7 .2.1 SSTL 3 Supply Voltage andLogic Input Levels SSTL_3 Output Buffers
Contents 93 94 96 98 98 100 103 104 107 107 108 109 110 110 1i1 111 112 113 114 117 117 123 125 129 129 129 131 136 138 140 141 142 143 145
Contents 7.2 .2 SSTL 2 SSTL_2 for Single-Ended Inputs and Outputs SSTL_2 for Differential Inputs and Outputs Illustration of SSTL_2 Thresholds Comparison of SSTL_2 with LVTTL SSTL_2 Design Example -DDR SDRAM Memory Subsystem 7.2.3 SSTL 18 7 .2.4 Summary of SSTL 7.3 Exercises Chapter a Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm) 8.1 A Fast Technology - Edge Rates of 20 ps at 12 Gbps? 8.1 .1 The ECL Families 8.1 .2 ECL Vendor Products 8.1 .3 Comparison of Several ECL family members Power Consumption ofECL Family Devices 8.2 Basic Device Operation 8.3 The Two Major ECL Standards -10K and 100K 8.3.1 ECL Output Load Drive Characteristics 8.3 .2 The "10" and "100" Prefixes -Both Family and Standard 8.3.3 Five Kinds of ECL Family Outputs 8.4 Single-Ended and Differential Signaling 8.4.1 Standard ECL Interface: Differential Driver and Receiver Advantages and Disadvantages of Single-Ended and Differential Interconnects 8.4.2 Single-Ended Interface VBB Reference The voltage reference Source VBB Dedicated Single-Ended Input Structure Single-Ended Interface Between 10 and 100 Standards Voltage Transfer Curves 8.4.3 Differential Interface VIHCMR Differential Interface Between 10 and 100 Standards ECL Noise Margins 8,5 Component Nomenclature 8.6 The ECL Families and Their Characteristics 8.6.1 A Little MECL History
x111 148 148 150 151 151 155 156 160 161 165 165 167 167 169 169 171 172 174 175 175 175 176 176 176 177 178 178 179 179 180 181 181 181 183 184 184
AV
Contents
8.6.2 10K
184
8.6.3 10H
185
Dual Meaning ofIOH Prefix
185
8.6.4 100K
185
8.6.5 100H
186
100H Used rrs Designation fir Clock Drivers/Translators
186
Caution : IOH and 10011 Devices with "L" Suffix
May Use OtherPower 0ptions
186
Micrel's 10H and 100H
187
8.6.6 ECL, PECL, Psuedo ECL, NECL, LVECL, LVPECL, and LVNECL 197
300 Series ECL
187
Super-300K LCL
188
9300 and 9400 Series ECLIPECL
1,48
ON Semiconductor's GigaConvn Family (SiGe)
188
Hot Ssmpping PECL Risk: Powered Driver and Unlrowered Receiver
189
8.6.7 ECLinPS and Low Voltage ECLinPS
189
8.6.8 ECLinPS Lite, Low Voltage ECLinPs Lite, and ECL Lite
189
8.6.9 ECLinPS Plus, ECL Pro, ECLinPS Pro, and Low Voltage ECLinPS Plus 191
8.6 .10 Reduced Swing ECL (RSECL, RSPECL, RSNECL)
and Variable Outputs
191
Reduced-Swing ECL vs. Low Voltage ECL
193
8.7 Summary of the ECL Families
193
8.8 Exercises
l95
Chapter 9 Current-Mode Logic (CML) 9.1 CML Overview 9.2 CML Output Structure 9.3 CML Input Structure 9.4 ac- and dc-Coupled CML Circuits 9.5 XAUI Interface Standard 9.6 CML Design Considerations 9.6.1 Pre-Emphasis, De-Emphasis, Transmit Equalization, and Receive Equalization 9.6.2 ac Coupling Requires 81311[}13 Encoding or de-Balanced Signal 9.7 How CML and ECL Differ 9.8 SuperLite CML and GigaPro"'M CML 9.9 Vendor-Specific CML Examples 9.9.1 Texas Instruments' SN65CMLIOO 9.9.2 Texas Instruments' TLK2501 1.5 to 2.5 Gbps Transceiver
199 199 202 203 204 207 211 211 213 213 218 219 218 220
9.9.3 Maxim's MAX3900 3 .2 Gbps Adaptive Equalizer and Cable Driver
223
Adaptive Equalization
225
9,10 Summary of Current-Mode Logic (CML)
226
9 .11 Exercises
227
Chapter y o FPGAs --- 3.1.25 Gasps RocketfOs and HardCopy Devices 10.1 Industry Trends 10.2 Altera FPGAS and CPLDs 10.2 .1 Altera PPGAs with Embedded High-Speed Transceivers Stratix GX FPGAs with tip to 20 Channels of 3.1825 Gbps SerDes Meivury FPGAs with rip to 45 Gbps of Bandwidth 10.2.2 Altera HardCopy Devices Elimination of ASIC Risk HardCopy Devices Designed with Quartus 11 Software HardCopy Stratix and APEX Devices 10.2.3 High-Density FPGAs Stratix FPGAs APEX FPGAs 10.2.4 Low-Cost/High-Volume FPGAs Cyclone FPGAs ACEX FPGAs 10.2.5 Altera FPGAs with Embedded Processors Excalibur Devices 10.2.6 Altera CPLDs MAX 3000 CPLDs MAX 7000 CPLDs MAX 7000AE CPLDs MAX 7000B CPLDs MAX 70005 CPLDs 10,2.7 Configuration Devices 10,3 Xilinx FPGAs and CPLDs 10.3 .1 Virtex FPGAs 10.3 .2 Spartan FPGAs 10,3 .3 CPLDs CoolRuuner CPLDs XC9500 10.3.4 More About the Virtex-II Pro FPGA 10.3.5 Virtex-11 Pro RocketIO Multi-Gigabit Transceiver 10.3.6 The Virtex-TI Pro PowerPC 405 Processor Core PPC405x3 Hardware Organization
231 231 233 234 235 237 238 239 240 240 241 242 243 244 244 245 245 2,45 246 246 246 246 247 247 247 248 248 248 248 249 249 249 250 251 252
xvi
Contents
10.3 .7 Applications of the Virtex-11 Pro
253
Data Pines
253
Reducing PCB Cotnplaxity
254
10.3.8 Support of Communications Standards
254
System-on-a-Chip (SOC) Designs
254
Network Processing
255
Protocol Bridges
255
10.3.9 Other Features of Virtex-11 Pro Devices
255
Global Clock Networks
255
Single-Ended SelectIOrh{-Ultra Resources
256
LVDS 1/0
256
LVPECL 1/0
256
Block SelecIRAW,' Memory
256
Distributed SelectRAM Memory
256
Bitstream Encryption
257
Loopback
257
Digital Clock Managers (DCMs)
257
Digitally Controlled Impedance (DCI)
258
Double-Data-Rate (DDR)1/0
258
10 .3.10 IBIS and SPICE Models for Xilinx Devices
258
10.3.11 Xilinx intellectual property (IP) Cores
259
10.4 Exercises
260
Chapter 11 Fiber-Optic Components
263
11,1 Getting On Board with Optics
263
11 .1 .1 The Rationale for Optical Interconnects
263
11,1 .2 Optics in the Physical Design
264
11,1 .3 Modeling Optical Interconnects
265
11,2 Comparison of Copper and Fiber Transmission Media
265
11 .3 Application Space for High-Speed Optical Data Link Modules
267
11 .4 Using Fiber for the Short Haul
268
11 .4.1 User Beware
271
11 .5 The 10 Gbps X-Modules
272
11,5.1 Xenpak
273
Xenpak MSA
275
11 .5.2 Xpak
276
11 .5.3 X2 Module
277
11 .5.4 XFP Module
278
11 .6 PAROLI 2 Parallel Optical Link Modules and Backplane Optical Interconnects 279
11 .7 Dense-Wavelength-Division Multiplexing (DWDM)
283
Contents
11 .8 Trends in the Application of Fiber Optics 11 .8.1 Exciting Optical Devices 11 .8.2 PON Devices 11 .9 Optical Cable Applications 11 .10 Optical Internetworking Forum (OIF) 11 .11 Fiber-Optic Connectors 11 .11.1 Small Form Factor Connectors 11,11.2 InfiniBand Connectors 11 .12 Laser Safety 11 .13 Vendors and Organizations for Fiber-Optic Components 11 .14 Exercises
Chapter 12 High-Speed Interconnects and Cabling
12.1 SiliconPipe's 12.8 GHz to 40 GHz Interconnect Solutions 12,1 .1 Yosemite - 40 Gbps Backplane Channel Technology 12.1 .2 Sequoia - 20 Gbps Chip-to-Chip Channel Technologies 12.1 .3 Grand Canyon ---12 .8 Gbps Memory Channel Technologies
ChaniPlexer-High-Speed Menzoiy Channel
SeriPlexer-Next-Gen Meniony Channel Technology
12.1 .4 Limitations of Conventional Backplanes 12.1 .5 How SiliconPipe Technology Works
Backplanes Mennony Interconnects
12.2 High-Speed Connectors
12.2.1 Teradyne VHDM-HSD Connector Example
12,2.2 XAUI Connectors
12.2.3 InfiniBand Connector
12.3 High-Speed Cabling
12.3.1 Copper Cable Applications
12.3.2 InfiniBand Cabling
12.4 Cables and Connectors for LVDS
12,4.1 General Comments on Cables and Connectors
12,4.2
Cabling Suggestions 71visted Pair Tvin-Ax Cables Flex Circuit Ribbon Cable
12.4.3 Connectors 12.4.4 Cable Ground and Shield Connections 12.5 Exercises
XV11 283 284 286 287 288 288 288 289 290 291 292 295 295 296 297 298 298 298 298 300 300 302 302 303 304 305 305 305 305 306 306 307 307 307 308 308 308 310 311
Part 3 High-Speed Memory and Memory Interfaces
Chapter 13 Memory Device Overview and Memory Signaling Technologies
13.1 Overview and Trends
13 .2 A Quick Review of Memory Basics
13.2.1 Read/Write Memory
13.2.2 Static RAM
Static RAM Inputs and Outputs
Static RAM Tining
Synchronous SRAM
13.2.3 Dynamic RAM (DRAM)
Dynamic RAM Structure:
Dynatnic RAM Tuning
Synchronous DRAMS
FPM (Fast Page Mode) DRAM EDO DRAM (Extended Data Out DRAM) RLDRAM (Reduced Latency DRAM)
13.2.4 Special Application Memory Video RAM (VRAM)
Dual-Port Graphics Buffer
SGRAM (Synchronous Graphics RAM)
13.2.5 Read-Only Memory (ROM)
13 .2.6 Flash Memory
13 .2.7 ECC (Error-Correcting Code) Memory
13 .2.$
Banks and Ranks Batiks Ranks
13 .2.9 Memory Nomenclature
Speed Bin
13 .3 Memory Signaling Technologies
13.3.1 SSTL_18, SSTL_2, and HSTL (Class 11)
13.3.2 RSL (Rambus Signaling Level)
13 .3.3 DRSL (Differential Rambus Signaling Levels)
13 .3.4 QRSL (Quad Rambus Signaling Levels)
13.3.5 Octal Data Rate (ODR)
13 .4 Design Considerations in Use of Memory 13.4.1 Power Up and Initialization
Contents 313 315 315 319 319 320 320 321 323 325 325 327 329 330 331 331 331 331 331 332 332 333 333 334 334 334 335 336 337 337 337 338 339 340 340 340
13 .4.2 Slew Rate Control 13 .4.3 Drive Capability 13 .4.4 On-Die Termination (ODT) Modifying Terrninations "On-the-Fly" 13.4.5 Memory Power and Ground Planes 13.4.6 Memory Controllers 13.5 Summary of Memory Devices and Terminology 13.6 Exercises Chapter -14 Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation 14.1 DDR (Double Data Rate) SDRAM 14.1 .1 Differences Between SDRAM and DDR SDRAM Drferences in Functions and Specifications Differences in Connnands Dif ferences in Operation 7-aning 14.2 DDR2 (Double Data Rate 2, DDR-11) SDRAM 14.2.1 DRAM Architecture Changes DDR2 Array Definition DDR2 Page Size DDR2 Bank Accesses 14.2.2 On-Die Termination ODT WRITES ODTREADS Termination Values On-Die Termination Control in Active Mode On-Die Termination Control in Porver-Dotim On-Die Termination Control in SelfRefresh Off-Chip Driver (OED) Calibration 14.2.3 Additional Mode Register Changes Mode Register (MR) CAS Latency WRITE Latency Sequential Interleave Active Poiver-Down Mode Write Recovery &tendedMode Register (EMR) Additive Latency DQS Configuration Single/Differential Data Strobe Redundant DQS (RDQS) Output Disable
341 341 342 343 344 344 344 350 353 353 354 354 359 361 363 364 364 364 365 366 367 367 369 370 370 371 371 373 373 373 375 376 376 377 378 378 380 381 381 381
Contents
14.3 SPICE/IBIS Simulation of DDR-Ii SDRAM
382
14.3.1 SPICEABIS Simulations of DQ and DQS Pins
382
14.3.2 Clock Signal Integrity
387
14.4 Exercises
389
Chapter -i 5 GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM 15.1 Graphics Double Data Rate SDRAM (GDDR, GDDR2, GDDR3) 15.1.1 GDDR3 (Graphics DDR 3) GDDR3 Derdce Operation GDDR3 Power Consumption Calculations 15.1 .2 Terminology; GDDR SDRAM vs. DDR SDRAM 15.2 ZBT, NaBL, ZeroSB, and NtRAM SRAM 15.3 FCRAM (Fast Cycle RAM) 15.3.1 Network FCRAM 15.3.2 Mobile FCRAM Stacked MCP (Multi-Grip Package) 15.3.3 Consumer FCRAM The Low Ivtency of Consumer FCRAM Consroner FCRAM for SiP (System-in-a-Package) 15.3.4 Summary of FCRAM Features 15.4 SigmaRAM (IRAM) 15.4.1 The SigmaRAM Family 15.4.2 SigmaRAM Features 15,5 RLDRAM (Reduced Latency DRAM) 15 .5 .1 RLDRAM as a New Memory Standard for High-Speed Applications Networking Requirements Pmgrarnnrable ltnpedance Output Buffer 15 .5.2 RLDRAM I and RLDRAM 11 15.6 DDR SRAM (Double Data Rate SRAM - DDR, DDRII SRAM) 15.6.1 DDRII SRAM Specified by QDR Consortium 15.6.2 Comparison of DDRII SRAM and DDR-II SDRAM IIOs 15.7 Flash Memory 15.7.1 Flash Densities, Access Tithes, and Other Features 15.7.2 Cell Phone Applications 15.7 .3 NOR vs. NAND Flash 15.7.4 Significance of Block Size 15.7 .5 Read-While-Write (RWW) Flash
391 391 394 394 395 395 396 397 399 399 400 400 401 404 404 405 406 407 407 408 408 409 409 410 411 412 412 413 414 415 416 417
Contents
15.7.6 Page-Mode Flash Memory
Page Definition
15 .7 .7
How a Page-Mode Read Works Conilmring a Page-Mode Device to a Standard Device Requirements on a System Using Page-Mode Flash Burst-Mode Flash Memory
15.7.8 MirrorFlash and Multi-Level Cell (MLC)
15 .7 .9 Role of Software
15.7.10 Flash Interfaces
15.7.11 Flash Cards
15.8 FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive RAM)
15.9 Memory Selection Guide
15.10 Exercises
Chapter 16 Quad Data Rate (QDR, QDRI1) SRAM 16.1 Introduction to QDR 16.1.1 Choosing the Right SRAM 16.1.2 Address Rate 16.1.3 Write Data Placement 16.1.4 Clocking Design 16.2 QDR SRAM Clocking Scheme 16.2.1 The QDR Device 16.2.2 Using the Separate input and output Clocks 16.2,3 Latching Data at the Controller 16.3 Comparison of QDR with QDRII 16.3.1 QDRII and QDR Functional Differences 16.3.2 QDRIJ Features Data Valid Window ECho Clocks 16.3.3 Negative Hold Times 16.3.4 Impact of DLL on the Operating Frequency Range 16.3.5 Choosing Between Burst of 2 and Burst of 4 16.3.6 Compatibility Considerations Between QDRII and QDR 16.3.7 Typical Implementation in a System Write Tunings Read Tanings 16.3.8 Package 16.3.9 Output Impedance Control 16.3.10 Data Line Terminations QDR IBIS and HSPICE Models
XXI 417 418 418 419 420 420 421 422 422 423 424 425 425 429 429 430 433 433 434 435 435 436 437 438 440 440 441 441 441 442 443 443 443 444 445 447 447 447 448
16.3.11 Clamshell Design 16.4 Exercises Chapter -17 Direct Ramous DRAM (DRDRAM) 17.1 Direct Rambus DRAM""' (DRDRAM, RDRAM) 17.1 .1 RDRAM Memory 17.1 .2 The Memory Landscape 17.1 .3 Bandwidth and Latency Comparing RDRAM with SDRAM and DDR SDRAM Asstanptions for Comparisons Recd-World Performance : Bandwidth SDRAM Bank Conflict and Command Bus Bandwidth Limitations Real-World Performance : Latency 17.1 .4 System Cost: Memory Granularity 17.1 .5 System Cost: Pincount and Bandwidth 17.1 .6 Motherboard Layers and Power Dissipation 17.2 Long-Channel Design 17.2.1 Rambus Memory System 17 .2.2 Schematics of a 16-Bit, Long-Channel Rambus System 17 .3 Exercises s Chapter -1 Xtrerne Data Rate (XDR) DRAM, FIexPhase and ODR 18 .1 Introduction to XDR 18.1 .1 XDR DRAM 18.1 .2 XDR DRAM Summary Table 18,1 .3 DRAM Block Diagram 18 .1 .4 XDR System Overview 18.2 XDR Physical Layer 18.2.1 Signaling 18 .2.2 Clocking 18,2.3 Data Transfers 18,2.4 Address/Control Transfers 18 .2.5 XDR 310 Cell (XID) 18.3 XDR Logical Layer 18 .3 .1 Write Transaction 18.3.2 Read Transaction 18.4 Applications
Contents 448 449 451 452 454 455 456 456 457 457 458 459 459 460 460 461 461 463 468 471 471 472 473 473 475 476 476 477 478 479 480 481 482 4.82 482
Contents
XXIII
18 .4.1 The Gaming Console Solution
482
18.4.2 The HDTV/Consumer Solution
483
18.4.3 The PC Graphics Solution
484
18.4.4 The PC Main Memory Solution
484
18.5 Exercises
486
Part 4 Modeling, Simulation, and EDA Tools
489
Chapter -19 Differential and Mixed-Mode S-Parameters 491
19.1 S-Parameters Bridge the Gap Between Chips and Systems
492
19.2 The Rationale for Using S-Parameters
493
19.2.1 Package Measurements
494
19.3 Single-Ended S-Parameters
495
19.3.1 Introduction
495
19.3.2 Two-Port Network Theory
495
19.3 .3 Using S-Parameters
496
Derivation
497
19 .3 .4 Smith Chart Transformation
499
19.3.5 Advantages of S-Parameters
500
19.4 Differential and Mixed-Mode S-Parameters,
501
19.4.1 The Need for Differential and Mixed-Mode S -Parameters
507
19.4.2 Return Loss Measurement Example
508
19.4.3 Touchstone Format
510
19.5 Calibration
511
19.5 .1 Measurement Errors
511
19.5 .2 Removing test fixture Effects : Direct Measurement and De-Embedding 511
19.5 .3 Calibration Example: Using Direct Measurement to
Eliminate Test Fixture Effects
513
19.6 Exercises
516
Chapter 20 Time Domain Reffectometry (TDR), Time Domain Transmission (TDT), and VNAs
20.1 Time Domain Reflectometry (TDR)
20.1 .1 Introduction
20.1 .2
Single-Ended TDR Measurements TDR and Luml)ed Element Analysis TDR Resolxtion and Rise Time
519 519 519 520 522 522
XXIV
Contents
20.1.3 Differential TDR Measurements Differential and Odd-, Common- and Even-Mode Impedances
20.1 .4 Cables, Connectors, and Probes
20.1.5 Multiple Reflections and the True Impedance Profile
20.1 .6
Other TDR MEASUREMENT ISSUES Using Good Measurement Practices TDR Measurements of "Splits" and "Stubs"
20.1 .7 Frequency Domain and TDR
20.1 .8 Static Discharge Precautions
20.1 .9 Controlling Rise Time
20.1 .10 Example ofTDR Oscilloscope
20.2 Time Domain Transmission (TDT)
20.3 TDR and TDT Simulations for a Loaded BLVDS Backplane
20.3.1 Loading Effects of Connectors, Stubs, and ICs on the Backplane
20.3.2 Effect of Plug-In Card Stub Lengths
20.4 Vector Network Analyzer (VNA)
20.4.1 VNA Instrumentation Background
20.4.2 Network Analyzer Terminology : R, A, and B Channels vs. Port I and Port 2
20.4.3 The Differences Between VNAs, Scalar Network Analyzers (SNAs), and Spectrum Analyzers
20.4.4 Vector error correction of Systematic Measurement Errors
20.4.5 The Mathematics of Time and Frequency
20.4.6 20.4.7
Practical Comparison of TDR and VNA Measurements Frequency Domain Measurements Using TDR VNAs with Time Domain Capability
20.4.8 Comparison, Summary, and Recommendations 20,5 Exercises
Chapter 2 -1 Modeling with IBIS 21 .1 An Introduction to IBIS (110 Buffer Information Specification) Modeling 21 .1 .1 Introduction 21 .1 .2 About IBIS 21 .1 .3 History of IBIS 21 .1 .4 Golden Parser 21 .1 .5 Advantages of IBIS 21 .1 .6 Input Structure Model 21 .1 .7 Output Structure Model
524 525 527 528 531 531 531 532 534 534 535 536 536 536 538 540 540 541 542 544 545 546 549 550 550 551 555 555 555 556 556 557 557 557 557
Contents
XXV
21 .1 .8 The IBIS Model Generation Process 21 .1.9 IBIS Model Validation on a Simulator 21 .1 .10 Using SPICE to Model Multigigabit FPGA 110s and Pre"Emphasis 21 .1 .11 future trends of IBIS 21 .2 Example of an IBIS Model 21 .3 Exercises
Chapter 22 Mentor Graphics --- EDA Tools for High-Speed Design, Simulation, Verification, and Layout
22.1 Overview of Mentor Graphics High-Speed Tools
22.2 ICX
22.2.1 IS Analyzer Hierarchical Rides Entry and Managenrew
Analysis and Verification
System-bevel
Defintion and Analysis
1$.-Analyzer Major Benefits
22.2.2 IS_Floorplanner
Ilierarclzical Rides Management
Hierarchical Floorplanning A Complete Wlzat-fAnalysis Environment Analysis and Verification Major IS_Floorplanner Benefits
22.2.3 IS Multiboard System-Level PCB Design
Systemi-Level Definition
Analysis and Verification
22.2.4
IS-Optimizer Electrically Driven Interconnect Design Hierarchical Rides Entry and Management
Interconnect Optunization Interactive Syndiesis
Underlying Architecture
22.2.5 ISSynthesizer Electrically Driven Interconnect Design
Hieranrldcal Rides Entry and Management Interconnect Optiuzizatiort Interactive Synthesis
Powerful Underlying Teclinology
22.3 Tau
22.3.1 Circuit Timing Methods and Symbolic Timing
Timing Methods
559 559 560 561 561 569 571 571 573 575 57.5 575 576 576 576 576 577 577 577 578 578 578 578 578 580 580 580 580 581 581 581 581 5231 582 582 582 583 583 584
xxvi Symbolic 7hning Analysis with 7itu Timing Models Using Tan in a Workflow Conchrsion 22.4 HyperLynx 22.4.1 HyperLynx GHz Complete S1 and EMC Analysis Suite LineSbn GHz 22.4.2 HyperLynx EXT Complete S1 and EMC Analysis Suite LineShn EX7' 22.5 Mentor Graphics Field Solvers Used in ICX and HyperLynx 22.5.1 Introduction 22.5.2 Geometry Problem Entry and Discretization 22.5.3 Speed and Accuracy 22.5.4 The Method of Moment Technique 22.6 The Expedition Series and Design Flow 22.6.1 DxDesigner Design Reuse Integration with the Enterprise Constraint-Based Design. Variant Managentent 22.6.2 Expedition PCB AwoActive Technology Dynanuc Area Fills Rules by Area Multiplow with Variable Via Patterns Dynamic Hazard Review ECOs with Expedition PCB and the Expedition Series Constraint Definition 59 Net Tutting 9 Differential Pair Routing Advanced Interconnect Routing TeaniPCB Design Reuse DMS -- Design data management 22.6.3 FPGA BoardLink FPGA On-Board Reducing Design Times for FPGA/PCB hrtegration FPGA Device Support 22.6.4 HDL Designer Series (FPGA Advantage) The Design Manager Provides Complete Design Visibility Tusks Support Repeatable Design Process
Contents 585 585 586 587 587 588 589 589 589 590 590 591 591 592 593 593 594 594 595 596 596 596 596 597 598 598 598 599 599 599 599 599 601 601 601 601 602 602 603 603 603 603
Contents
xxvff
Mix Text, Tabular ; and Graphical Editors .for Varying Design Requirements 604
lrrrerfaced-Based Design Methodology Rapidly Defbres Design Structure
604
hrfuilive Graphical Editors
605
Flexible ModuleWare Logic Generator
605
Practical IP and Design Reuse
605
22 .6.5 ModelSim (FPGA Advantage)
606
High-Performance, Trilingual verification Environment
606
Verilog 2001/SysteniVerilog
607
22 .6.6 Quiet Expert
607
EMC-Based Design Ride Checker
607
Easy Viewing of Results
608
Custonrizable Flow Control
609
22.7 Signal Integrity and Timing Models
610
22.7.1 Signal Integrity Models
610
Isis
610
SPICE
610
VHDL-AMS
610
22 .7.2 Tinning Models
611
TDML
611
STAMP
612
TDML vs. STAMP
613
22,8 Use the Right Models for Simulation of Multigigabit Channels
613
22 .8.1 Introduction
613
22.8.2 The Circuit under Study
614
22 .8.3 Model Reduction
616
22 .8.4 Package Model Simplification
617
Package Element Elimination
619
IBIS RLC Package
619
S-Paranreler Package Model
619
22 .8.5 Behavioral Modeling
620
22.8.6 Conclusion
622
22.9 Exercises
623
Part 5 Design Concepts and Examples
625
Chapter 23 Advances in Design, Modeling, Simulation,
and Measurement Validation of High-Performance
Board-to-Board 5-to-10 Gbps Interconnects
627
23.1 Introduction
627
23.2 Modeling Methodology
630
Contents
23.2.1 Major System Elements
630
PCB Trace Modeling
632
Connector Design
635
Breakout Region (BOR) Modeling
636
Was
639
23.3 Simulation
639
23 .3 .1 HSPICE W-Element Issues
640
Passivity in Frequency Domain Network Measurement and Simulation
640
Managing Error in Frequency Domain Network Parameters
641
Error-Induced Nonpassivity ofNetwork Parameters
642
Correcting ErrorInduced Nonpassivity in S-Parameter Network Models
644
23.4 Measurement
648
23.4.1 The Design and Need for High-Accuracy Test Boards
648
High-Bandwidth SMA Launch
648
Isolation of Traces Prior to Final Inch
649
Reference Structures
649
23 .5 Measurement Accuracy Issues
649
23.5.1 SMA Launch
650
23.5 .2 Traces
652
23.5 .3 Measurements
652
23 .6 Frequency Domain Measurement
652
23 .6 .1 Calibration
652
23 .6 .2 Measurements
652
23 .6 .3 Time Domain Measurements
652
23 .6 .4 Application Proof
653
23.7 Validation of Material Parameters
653
23 .7 .1 Terms
654
23 .7 .2 Some Extracted Data
655
23 .7.3 Overview of Characterization Methods
655
23.8 Stripline Measurements
656
23 .8 .1 Stackup
656
23.8.2 de Resistance
656
23 .8 .3 Characteristic Impedance and Delay
658
23.9 Stripline Results
658
23,9.1 Effective Relative Dielectric Constant
658
23.9.2 total losses for Stripline
659
23 .9.3 Loss Tangent Estimation
660
23.10 Calculation Methods and Validation
664
23.10.1 Comparison of Connector Simulations with
and without Final Inch and Discussion of Advantages
665
Contents
23.10.2 SMA Test Trace Comparisons, Modeled vs . Measured 23.11 Conclusions 23.12 Exercises
Appendix 23.A Generalized N-Port, Mixed-Mode S-Parameters 23.A.1 Why Do We Care? 23.A.2 Development of N-Port, Mixed-Mode S-Parameters
Chapter 24 IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers 24.1 Introduction 24.2 IBIS Models for High-Speed Fiber-Optic Transceivers 24.3 The Electrical Board Description (EBD) File 24.4 Verification of IBIS Models 24.5 IBIS Models in "Real-World" Circuits 24.6 Signal Integrity case study 24.7 Summary 24.8 Exercises
Chapter 25 Designing with LVDS
25.1 Layer Stack-Up and PCB Design
25.2 PCB Board Layout Tips
25.2.1 PC Board
25.2.2 Traces
25.2.3 Differential Traces
25.2.4 Termination
25.2.5 Unused Pins
25.2.6 Probing LVDS Transmission Lines
25.2.7 Loading LVDS 110 - Preserving Balance
25.2.8 Results of Good vs. Bad Design Practices httpedance Mismatches
25.2.9 Crosstalk Between TTL and LVDS Signals
25 .2.10
Lowering Electromagnetic Interference (EMI) LVDS and Lmver EMI electromagnetic radiation of Differential Signals Design Practicesfor Lose EMI
EMI Test Results
xxfx 670 673 674 676 676 677 681 681 682 684 685 687 690 692 693 695 695 697 698 699 700 703 704 705 705 705 705 706 707 707 708 710 713
xxx 25 .2.11 Ground Return Paths 25 .2.12 Cable Shielding 25 .2.1 :3 Common-Mode Noise Rejection 25.3 LVDS Configurations 25.4 Failsafe Biasing of LVDS 25.4.1 LVDS Failsafe Conditions 25.4.2 Boosting Failsafe in Noisy Environments 25.4.3 Choosing External Failsafe Resistors 25.4.4 Power-Off High Impedance Bus Pins 25.5 Bye Pattern Test Circuit 25.5 .1 Eye Pattern Test Procedure 25.5 .2 Eye Pattern Test Results and data points 25.6 BER Test Circuit 25.6.1 BER Test Procedure 25.6 .2 BER Tests and Results 25.7 Exercises Chapter 26 Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers 26.1 Introduction and the DS92LV 16 (2.56 Gbps) 26.2 Bus LVDS SerDes Architecture 26.3 Bus Topologies/Applications 26.3.1 Point-to-Point 26 .3.2 Multidrop 26.4 Backplanes 26 .4.1 Point-to-Point 26.4.2 Multidrop 26.4.3 Termination 26.5 PCB Recommendations 26.6 Cables and Connectors 26.6.1 Cables 26.6.2 Connectors 26.7 Power and Ground 26.7.1 General Recommendations 26.7.2 DS92LV l6 Bypassing Recommendations PVDD/PGND PLL Supply AVDD/AGND LVDS Supply Comparing Power Consumption
Contents 715 716 716 719 720 720 721 721 723 723 723 725 727 728 728 729 733 733 735 736 738 738 739 739 739 739 740 742 742 743 743 743 744 744 745 745
Contents
DVDDIDGND Digital Supply
746
26.7 .3 Power-Up Sequencing
746
26 .8 Clocking
746
26 .8 .1 Transmit Clock (TCLK)
746
26.8 .2 Receiver Reference Clock (RefCLK)
747
26.8 .3 Receiver Output Clock (RCLK)
747
Clock .litter
747
26.9 Inputs and Outputs
748
26.9 .1 Unused LVTTL Inputs
748
26.9 .2 Floating Bus LVDS Receiver Inputs and Failsafe
748
26.9.3 Receiver CMOS Output Drive
748
26.10 Evaluating the DS92LV 16
749
26 .10,1 Evaluation Board
749
26 .10.2 Probing Bus LVDS Signals
749
26.11 Loopback Testing
750
26.11,1 Local Loopback
750
26.11 .2 Line Loopback
751
26.12 Lock to Random Data vs. SYNC Patterns
751
26 .12.1 SYNC Patterns
751
26,12 .2 Lock to Random Data
751
26.12.3 Sending SYNC Patterns vs. Lock to Random Data
752
26.12.4 Once Lock Is Achieved
752
26.13 Interconnect Jitter Margin
752
26.13,1 Interconnect Jitter Mask
752
26 .13 .2 Validating Signal Quality
754
26 .13 .3 Steps to Construct a Jitter Mask
754
26 .13 .4 Alternative Jitter Estimates Using Only the Device Datasheet
758
26.14 Troubleshooting
759
26.15 Quad 2.5 Gbps (I0 Gbps) Serializer/Deserializer (SerDes)
760
26.15 .1 General Description
760
26 .15 .2 DS25C400 Features
761
26 .15 .3 Selectable Pre-Emphasis to Improve Signal Quality
761
26.15.4 Equalization .Filtering at Receiver
762
26.16 Eight-Channel 10:1 Serializer for 5.28 Mbps
763
26.16 .1 Serializer General Description
763
26.16 .2 Serializer Features
763
26 .16.3 Serializer Functional Description
765
Initialization
765
XXXII
Contents
Data Transfer ResynclrronIzation @Speed Test Power-Down TRI-STATE 26.16.4 Serializer Application Information Using the DS92LV8028 Power Considerations PC13 Layout and power system Considerations Transmission Media Termination DS92LV8028 BUDS Serializer Bypass Recommendations Grounds 26.17 Exercises Chapter 27 WarpLink SerDes System Design Example 27.1 WarpLink Design Overview 27.2 Introduction 27.2.1 WarpLink 2.5 Quad Device 27 .2.2 WarpLink Reference Design Platform Goals 27 .2.3 WarpLink Reference Design Platform Overview Areltitectural Overview Backplane Line Card Switch Cant Test Card 27.3 detailed design Descriptions 27.3, I WarpLink Reference Backplane BackplanelCltassis Design Considerations WarpLink Backplane Physical Description Backplane Design Rules and Layer Stackup 27.3.2 Line, Switch, and Test Cards Daughter Card Design Considerations Test Card and Line Card Layer Stackups 27.4 WarpLink Signal Integrity HSPICE Simulations 27 .4.1 WarpLink Gigabit Simulations 27 .4.2 WarpLink Interconnect Impedance Profile 27 .4.3 WarpLink Reference System Clock Simulations 27.5 Descriptions of Passive Signal Integrity Measurements 27.5.1 Time Domain Reflectometry (TDR)
766 766 767 768 768 768 768 769 769 770 770 770 770 771 775 775 776 776 778 779 779 781 782 783 78,3 783 783 783 786 787 788 788 788 788 788 792 795 796 796
Contents 27.5.2 Differential Time Domain CrosstaIk 27.5.3 Eye Diagrams 27,5.4 Time Domain Test Equipment 27.6 Passive Measurement Results 27.6.1 TDR Results 27.6.2 Eye Diagram Measurement Results 27.7 Active Measurement Results 27.7.1 Test Setup 27,7.2 Eye Diagrams from Slot 8 to Slot 1 27.7 .3 Eye Diagrams from Slot 7 to Slot 1 27.8 Summary and Conclusions 27.9 Exercises Part 6 Emerging Protocols and Technologies Chapter 28 Electrical Optical Circuit Board (EOCB) 28.1 The Photonic PCB Industry and Development Programs 28.2 Optoelectronic Printed Circuits Based on HDI-Microvia Technology 28.2.1 Benefits ofHDI 28.2.2 Microvia Technologies 28.2.3 Use of Microvias in PCBs Better Electrical PerforniancelSignal Integrity Improved RF11EMIlESD 28.2.4 Photonics and Electrical Performance 28.3 Photonics and Waveguides 28.3.1 Optical Waveguide Materials 28.3.2 31) fabrication techniques Terahertz Photonics' Truemode Back-plane Electrical Optical Circuit Board PolyGuide Tppcat 28.33 New Components 28 .3 .4 3D Assembly Techniques 28.3 .5 NTT, University of Texas, and REP 28.4 Conclusion 28.5 Exercises
797 797 797 798 798 798 800 801 802 802 803 804 80'7 809 809 810 811 811 812 812 812 812 813 815 817 818 819 821 823 824 825 825 827 828
XX%Iv Chapter 29 RapidlO 29.1 Rapidl0; The Interconnect Architecture for High-Performance Embedded Systems 29.2 RapidlO Is Now an International Standard 29.3 Embedded System Development 29.3.1 Why RapidIO? 29.3.2 Interconnect Landscape 29.3.3 Where Will It Be Used? 29.3.4 Philosophy 29.4 RapidlO Protocol Overview 29.4.1 Packets and Control Symbols 29.4.2 Packet Format 29.4.3 Transaction Formats and Types 29.4.4 Message Passing 29.4.5 Globally shared memory 29.4.6 Future Extensions 29.4.7 Flow Control 29.5 Physical interface 29.5.1 Parallel Electrical Interface 29.5.2 The Serial RapidIO Controller 29.5.3 Link Protocol 29.5.4 Enhanced Flow Control 29.5.5 PCS and PMA Layers 29.5.6 Electrical Interface 29.6 Maintenance and Error Management 29.6.1 Maintenance 29 .6.2 System Discovery 29.6.3 Error Coverage 29.6.4 Error Recovery 29 .7 Performance 29.7.1 Packet Structures 29.7.2 Source Routing and Concurrency 29 .7.3 Packet Overhead 29.7.4 Bandwidth 29.7.5 Operation Latency 29 .8 Summary 29.9 Exercises
Contents 829 829 830 830 831 832 833 835 836 836 837 838 839 840 840 841 842 842 843 843 844 844 845 845 845 84.5 846 846 846 846 847 847 847 849 849 849
Contents Chapter 30 PCt Express and ExpressCard 30.1 PCI Express as Next-Generation 1/0 30.2 PCI Express Architecture Overview 30.3 PCI Express Architecture 30.3.1 Physical Layer 30.3.2 Link Layer 30.3.3 Transaction Layer 30.3.4 Software Layers 30.3.5 Mechanical Form Factors ExpressCard 30.4 Development Timeline 34.5 Summary 30.6 Exercises Part 7 Lab and Test Instrumentation Chapter 31 Electrical and Optical Test Equipment 31 .1 Oscilloscopes 31 .1.1 Classes of Oscilloscopes- Real-Time vs. Equivalent-Time 31 .1.2 Real-Time Oscilloscopes 31 .1.3 Equivalent-Time Oscilloscopes 31 .2 Bit Error Ratio Testers (BERTs) 31.3 Pulse Generators 31 .4 Jitter Analyzers 31 .5 logic analyzers 31 .6 Characterizing Optical Systems 31 .6.1 Optical Spectrum Analyzer (OSA) 31 .6.2 Photodetection Using Equivalent-Time Oscilloscope 31 .6.3 Optical Modulation Amplitude (OMA) and Extinction Ratio 31 .6.4 Power Meters 31 .6.5 Characterizing Fiber Properties 31 .6.6 Optical Receiver Sensitivity 31 .6.7 Optical Amplifiers 31 .6.8 Multi-Wavelength Meter 31 .6.9 Reference Receiver 31 .7 Test Equipment Specifications 31.8 Exercises
xxxv 851. 851 854 857 857 858 859 859 860 860 862 862 862 865 867 868 868 868 870 873 876 877 879 880 880 881 882 882 882 882 883 883 884 885 885
Acronyms References About the Author Index
Contents 887 893 908 909

T Granberg

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