Porous silicon masking by silicon oxide and hydrogen ion implantation, HEM PERES, E GALEAZZO, MOS DANTAS

Tags: silicon oxide, PS, PECVD, anodization, ion implantation, RTA, mask, Porous Silicon, silicon oxide layer, R. Kr�ger, G. Lerondel, Hydrogen ion, patterning, depth profile, PS formation, Luciano Gualberto, implantation, R. Romestain, PECVD silicon oxide, sensor applications, thick oxide layer, Cross section, thermal oxide, silicon membrane, Thin Solid Films, A. M. Gu� B. Fraisse, Silicon quantum wire, A. Fouracan, T. Taliercio, E. Massone, M. Dilhan
Content: Porous Silicon Masking by Silicon Oxide and hydrogen ion Implantation HENRIQUE E. M. PERES1, ELISABETE GALEAZZO2, MICHEL O. S. DANTAS AND Francisco Javier RAMIREZ-FERNANDEZ3 Sensores Integrбveis e Microssistemas - SIM group, Laboratуrio de Microeletrфnica Departamento de Engenharia de Sistemas Eletrфnicos - PSI, Escola Politйcnica - Universidade de Sгo Paulo Av. Prof. Luciano Gualberto, travessa 3, No 158 - CEP 05508-900 - Sгo Paulo - SP - Brazil Phone: (55)(11) 3818-5310 FAX: (55)(11) 3818 5585 http://sim.lme.usp.br [email protected], [email protected], [email protected]
Abstract A comparative study between two techniques for porous silicon (PS) patterning is presented: a thick silicon oxide layer used as mask and the other is a new possibility for masking areas that is obtained by hydrogen ion implantation combined with adequate annealing conditions. Tested oxide masks were a PECVD silicon oxide layer 2.5 µm thick or a thermal silicon oxide layer 2 µm thick. Test geometries were essentially constituted by stripes raging from 20 to 50 µm width. Obtained structures were examined by scanning electron microscopy (SEM) technique and showed that PECVD and thermal oxide masks induce non-uniformity of PS formation next to stripes borders. Hydrogen ion implanted "mask" resulted in an effective anodization blocking and isotropic PS formation under mask borders, so this alternative technique has proven its usefulness for PS patterning and for silicon membranes microfabrication. 1. Introduction Porous silicon (PS) has been a promising material in several microelectronics fields due to its characteristics such as: PS has a very high specific area (useful for gas sensors); strong visible photoluminescence (for light emitting devices); controllable refractive index (for general optoelectronic applications) and a simple and cheap obtaining and etching (for use as sacrificial layer in microelectromechanical Systems - MEMS fabrication) [1-4]. Normally, PS is obtained by silicon anodization in an electrochemical cell containing HF solution as electrolyte. For integration of PS structures with microelectronic devices, micrometric definition of PS areas is necessary. As the patterning of PS areas after its formation is incompatible with other microelectronic processes, then several alternatives for patterning PS before its formation are proposed [5]. All these techniques involve the "blocking" of anodization current on silicon surface regions where PS is not desired.
In this work, a comparative study between two alternatives for PS patterning is conducted. The first one is a mask formed by thick silicon oxide that was obtained by "plasma enhanced chemical vapor deposition" (PECVD) process or by thermal growth of silicon oxide [6]. The main problem of this kind of mask is a limitation of anodization process time due to the high etch rate of oxide into HF solution. The second patterning alternative proposed is a mask formed by hydrogen ion implantation over p-type silicon substrate, combined with rapid thermal annealing (RTA) [7]. Such procedure can creates a buried high resistivity layer due to damaging of silicon lattice and electrical neutralization of boron donor sites by hydrogen [8-9]. So, this second process was evaluated as a new technique to mask PS formation. 2. Materials and Methods Test geometry designed was essentially composed by parallel stripes of PS, ranging from 20 to 50 µm in width. Starting material was p-type silicon, <100> orientation with = 5 cm. Then, three alternatives for patterning were used, as follows: 2.1. PECVD Silicon Oxide Mask - Thermally grown SiO2 about 0.5 µm thick, ambient = dry O2; - Deposition of 2.5 µm thick PECVD silicon oxide; (These steps were made in order to obtain an good quality oxide close to silicon surface and a thick silicon oxide layer above it rapidly obtained by PECVD technique). - PECVD oxide densification: T = 1200oC, time = 60 Minutes, ambient = dry O2 (to improve PECVD oxide quality); - Stripes definition by conventional photolithography; - Al back deposition and alloy for electrical contact; - Selective areas PS formation by anodization process: J = 20 mA/cm2, time = 10 minutes in HF and ethanol solution (1:1).
RESISTIVITY (cm) 11µm
- Rinse in deionized H20, ethanol and pentane sequence in order to minimize capillarity forces to prevent PS cracking.
2.2. Thermal Silicon Oxide Mask - Thermally grown SiO2 about 2.0 µm thick: T = 1200oC, time = 6 h, ambient = wet O2; - Stripes definition, Al back deposition and alloy, in the same manner as before. - Selective areas PS formation: J = 40 mA/cm2, time = 8 minutes in HF and ethanol solution (1:1) (and rinse as before).
2.3. Hydrogen Ion Implantation with RTA "Mask"
- Deposition of 2.5 µm thick PECVD silicon oxide (for ion implantation blocking); - Negative photolithography, so oxide remains only in the stripes regions; - Hydrogen ion implantation: Energy = 50 keV, dose = 1E16 H+/cm2; - Rapid thermal annealing (RTA): Plateau temperature and time: T = 450oC, time = 5 minutes, ambient = argon. (This step was utilized to anneal the ion implantation as well as Al alloy back the samples). - Total oxide etching; - Selective areas PS formation: J = 30mA/cm2, time = 30 Minutes in HF solution (and rinse as before).
3. Results and Discussion
Samples submitted to hydrogen ion implantation and RTA were firstly analysed by "spreading resistance probe" (SRP) technique so a depth profile of resistivity was obtained, as can be seen in Figure 1.
1E6
1E5
b
a
1E4
(H+ distribution)
(resistivity)
1E3
1E2
1E1
1E0
1E-1
0.0
0.2
0.4
0.6
0.8
1.0
DEPTH (µm)
Fig.1: SRP depth profile after hydrogen ion implantation and RTA. Also showed simulated hydrogen distribution (arbitrary units) just after implantation.
From SRP profile, one can verify the desired high resistivity buried layer around 0.65 µm depth with a resistivity about 1E5 cm (which is the equipment limit). For comparison, Figure 1 also shows depth profile
for hydrogen concentration (in arbitrary units) just after ion implantation simulated by TRIM software [10]. After the PS formation step, the surface and crosssection of the samples were examined by electron microscopy. A JEOL (JSM-5900LV) scanning electron microscope was used. Figure 2 shows a Cross section SEM image of PS stripe defined by PECVD oxide. Lateral PS formation under stripe border is c.a. 7 µm, that is the same order of PS thickness. The pronounced non-homogeneity of lateral PS formation can be attributed to the presence of two oxide layers used as mask and from the current concentration at the border of the masking layer.
7µm Fig. 2: Cross section SEM image of PS stripe patterned by PECVD oxide. Besides, PS thickness around 7 µm is lower than expected. This is because several defects in PECVD oxide structure increase the effective anodization area, lowering the current density in the electrochemical process. In the other silicon oxide masking alternative (thick thermal silicon oxide mask), the problem of oxide defects can be avoided. Furthermore, an improvement in the homogeneity of PS formation under stripes borders can be obtained; however, it is not isotropic, as observed in Figure 3. surface
Si
PS
Si substrate
Fig.3: Cross section SEM image of two neighbour PS stripes patterned by thermal oxide.
Figure 3 shows two neighbouring PS stripes. The permanence of a thin silicon vertical wall and a thin superficial silicon platform beneath oxide can be seen, suggesting the pathway of the anodization current. An important aspect that can be considered when PECVD or thermal oxides were used as anodization mask, is the high etch rate of silicon oxide in HF solution. This requires a thick oxide layer, which can induce considerable stress and structure deformations. Figure 4 shows the sample patterned by thermal oxide, after total PS etching in KOH solution. A little bending of silicon membrane about 500 nm thick cam be verified.
Surface
For neighbouring stripes (Figure 6), one can verify a good definition of remaining superficial silicon layer c.a. 500 nm in thickness. When PS is removed (by KOH etch), it is possible to verify no deformation in the silicon membrane (Figure 7), so this "buried mask" could be useful for micromachining microstructures.
Si substrate PS removed
Si PS
Si membrane
Fig. 6: Cross section SEM image of two neighbour PS stripes patterned by hydrogen ion implantation and RTA.
Fig.4: Cross section SEM image of remaining silicon after PS etching of two neighbour stripes patterned by thermal oxide (image is upside-down in relation to Figure 3).
Results for PS patterning by hydrogen ion
implantation and RTA are shown in Figures 5, 6 and 7.
From Figure 5, a very homogeneous PS formation can be
verified under stripes borders. PS thickness and lateral formation are c.a. 17 µm, showing the anodization is also
Si
isotropic.
PS removed
Fig. 5: Cross section SEM image of a PS stripe patterned by hydrogen ion implantation and RTA. Another aspect to be pointed out is the good regularity of superficial silicon layer on the stripes borders.
Fig.7: Cross section SEM image of remaining silicon membrane after PS etching on sample patterned by hydrogen ion implantation and RTA. Additionally, hydrogen ion implanted mask has no time limitations in HF solution. 4. Conclusions Performance of two alternatives for PS patterning were compared. From results, it is possible to point out the following advantages an disadvantages of proposed "hydrogen ion implantation + RTA" procedure for PS masking:
Advantages: · Better mask uniformity and efficiency than PECVD oxide. · Very homogeneous and isotropic PS formation even beneath mask borders. (PECVD oxide and thermal oxide masks provoke non-homogeneous PS formation under mask borders, although thermal oxide induces better PS uniformity and thickness control than PECVD oxide). · Due to isotropic formation of PS beneath mask borders, silicon membranes can be obtained. · There is no time limitation into HF solution. This way, thick PS layers can be obtained (for sensors or optical devices applications, for exemple) and, additionally, silicon membranes above deep cavities can be fabricated (for MEMS applications). · Remaining superficial silicon membrane has good uniformity and no deformation, what is very important to build microstructures. · It is possible to obtain thin silicon membranes (smaller than 1µm) with good uniformity. Membrane thickness can be controled by hydrogen ion implantation and RTA processes parameters. Disadvantages: · Ion implantaton an RTA process sequence is more complicated and requires more processing time than usual oxidation step. · For microstructures fabrication, proposed sequence, including PS anodization step, is more complicated than usual wet etching. · Due to isotropic PS formation beneath mask borders, if deep PS layer is desired, then large lateral area is needed. · Silicon mask areas are damaged by ion implantation process. Electronic devices placed on these areas have limited performance, so it is very important to recover silicon crystalline structure. SRP profile just after RTA step and results from previous work [8] indicates that this desired condition can be reached. This way, hydrogen ion implantation with RTA is a promising procedure to allow new applications for porous silicon integration with sensors and electronic devices, as well in the MEMS microfabrication field. Acknowledgements We would like to thank the facilities offered by the Laboratуrio de Microscopia Eletrфnica at LNLS, Campinas, Brazil, for the electron microscopy work performed with the JSM-5900LV microscope, Novos Materiais e Dispositivos group from LME (PECVD growth) and LSI for RTA processes.
References:
[1] L.T. Canham, Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers, Applied Physics Letters, vol. 57, n.10, (1990), p.1046-1048.
[2] T. Taliercio, M. Dilhan, E. Massone, A. M. Guй, B. Fraisse, A. Fouracan, Realization of porous silicon membranes for gas sensor applications. Thin Solid Films, vol. 255, (1995), p. 310-312.
[3] I. Mihalcescu, G. Lerondel, R. Romestain, Porous silicon anisotropy investigated by guided light. Thin Solid Films, vol. 297, (1997), p. 245-249.
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[6] Galeazzo, E., Salcedo, W.J., Peres, H.E.M., Ramirez-Fernandez, Porous Silicon patterned by hydrogen ion implantation. sensors and actuators, B, v.76, issue 1-3, p. 343-346, 2001.
[7] Dantas, Michel. Otimizaзгo do processo de obtenзгo do silнcio poroso por processo eletroquнmico e sua obtenзгo em бreas seletivas. Trabalho de conclusгo de curso (Materiais, Processos e Componentes Eletrфnicos) ­ Faculdade de Tecnologia de Sгo Paulo (FATEC), 2001.
[8] H. E. M. Peres, F.J. Ramirez-Fernandez, High Resistivity Silicon Layers Obtained by Hydrogen Ion Implantation. Brazilian Journal of Physics, vol. 27/A, n. 4, (1997), p.237.
[9] J.I. Pankove, N. M. Johnson, Hydrogen in
Semiconductors.
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HEM PERES, E GALEAZZO, MOS DANTAS

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